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    Method and system for a multi-stage interconnect switch
    31.
    发明申请
    Method and system for a multi-stage interconnect switch 有权
    多级互连开关的方法和系统

    公开(公告)号：US20050041637A1

    公开(公告)日：2005-02-24

    申请号：US10920789

    申请日：2004-08-17

    Applicant: Jan Bialkowski ,  Wing Cheung

    Inventor： Jan Bialkowski ,  Wing Cheung

    IPC: H04L12/28 ,  H04L12/56

    CPC classification number: H04L49/1515 ,  H04L45/00 ,  H04L45/30 ,  H04L49/3018

    Abstract: An interconnect switch stores data messages received from one or more source devices and prioritizes the data messages received from each source device based on the order that the data messages were received from the source device. For each available destination device associated with the interconnect switch, the interconnect switch identifies the data messages with the highest priority that are to be routed to the available destination device and selects one of the identified data messages for the available destination device. The interconnect switch then routes the selected data messages to the available destination devices.

    Abstract translation: 互连交换机存储从一个或多个源设备接收的数据消息，并且基于从源设备接收数据消息的顺序来优先从每个源设备接收的数据消息。 对于与互连交换机相关联的每个可用目的地设备，互连交换机识别要被路由到可用目的地设备的具有最高优先级的数据消息，并且为可用目的地设备选择所识别的数据消息中的一个。 然后，互连交换机将所选择的数据消息路由到可用的目的地设备。

    Method and apparatus for avoiding control reads in a network node
    34.
    发明授权
    Method and apparatus for avoiding control reads in a network node 失效
    用于避免网络节点中的控制读取的方法和装置

    公开(公告)号：US5922046A

    公开(公告)日：1999-07-13

    申请号：US712736

    申请日：1996-09-12

    Applicant: Robert E. Thomas ,  Douglas M. Washabaugh ,  Peter J. Roman ,  Wing Cheung

    Inventor： Robert E. Thomas ,  Douglas M. Washabaugh ,  Peter J. Roman ,  Wing Cheung

    IPC: G06F11/30 ,  H04L12/56 ,  H04L29/06 ,  H04Q11/04 ,  G06F17/00

    CPC classification number: H04L47/522 ,  G06F11/3006 ,  G06F11/3027 ,  G06F11/3055 ,  G06F11/3096 ,  H04L29/06 ,  H04L47/521 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9036 ,  H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5635 ,  H04L2012/5658 ,  H04L2012/5679 ,  H04L2012/5681

    Abstract: A mechanism for avoiding the initiation of control read transactions on a system bus coupling a host system having a host memory and an interface connected to a peripheral unit as data is moved between the host system and the peripheral unit is presented. Control information associated with data memory portions in host memory is written to the interface for data memory portions storing outgoing data and data memory portions to receive incoming data. The interface includes a controller for moving data between the host memory and the interface by first obtaining the control information for the associated data portions. The interface writes status reports in association with the movement of data between the interface and the host memory via the system bus. The mechanism thus enables data transfers to occur via the system without the initiation of control reads in absence of an exception condition.

    Abstract translation: 提出了一种用于避免在系统总线上启动控制读取事务的机制，该系统总线耦合具有主机存储器的主机系统和连接到外围单元的接口，因为数据在主机系统和外围设备之间移动。 将与主机存储器中的数据存储器部分相关联的控制信息写入存储输出数据和数据存储器部分的数据存储器部分的接口以接收输入数据。 接口包括控制器，用于通过首先获得相关联的数据部分的控制信息来在主机存储器和接口之间移动数据。 该接口通过系统总线写入与接口和主机存储器之间的数据移动相关联的状态报告。 因此，该机制使得能够在没有异常条件的情况下通过系统进行数据传输而不启动控制读取。

    Longest prefix match scheme
    35.
    发明授权
    Longest prefix match scheme 有权
    最长前缀匹配方案

    公开(公告)号：US08880494B2

    公开(公告)日：2014-11-04

    申请号：US13284829

    申请日：2011-10-28

    Applicant: Jian Liu ,  Philip Lynn Leichty ,  How Tung Lim ,  John Michael Terry ,  Mahesh Srinivasa Maddury ,  Wing Cheung ,  Kung Ling Ko

    Inventor： Jian Liu ,  Philip Lynn Leichty ,  How Tung Lim ,  John Michael Terry ,  Mahesh Srinivasa Maddury ,  Wing Cheung ,  Kung Ling Ko

    IPC: G06F17/30 ,  H04L12/743 ,  G06F7/02 ,  H04L12/745

    CPC classification number: G06F7/02 ,  H04L45/7457 ,  H04L45/748

    Abstract: A LPM search engine includes a plurality of exact match (EXM) engines and a moderately sized TCAM. Each EXM engine uses a prefix bitmap scheme that allows the EXM engine to cover multiple consecutive prefix lengths. Thus, instead of covering one prefix length L per EXM engine, the prefix bitmap scheme enables each EXM engine to cover entries having prefix lengths of L, L+1, L+2 and L+3, for example. As a result, fewer EXM engines are potentially underutilized, which effectively reduces quantization loss. Each EXM engine provides a search result with a determined fixed latency when using the prefix bitmap scheme. The results of multiple EXM engines and the moderately sized TCAM are combined to provide a single search result, representative of the longest prefix match. In one embodiment, the LPM search engine supports 32-bit IPv4 (or 128-bit IPv6) search keys, each having associated 15-bit level 3 VPN identification values.

    Abstract translation: LPM搜索引擎包括多个精确匹配（EXM）引擎和中等大小的TCAM。 每个EXM引擎使用前缀位图方案，允许EXM引擎涵盖多个连续的前缀长度。 因此，代替覆盖每个EXM引擎的一个前缀长度L，例如，前缀位图方案使每个EXM引擎能够覆盖具有前缀长度为L，L + 1，L + 2和L + 3的条目。 因此，较少的EXM引擎潜在地未充分利用，这有效地减少了量化损失。 当使用前缀位图方案时，每个EXM引擎提供具有确定的固定延迟的搜索结果。 多个EXM引擎和中等大小的TCAM的结果被组合以提供单个搜索结果，代表最长的前缀匹配。 在一个实施例中，LPM搜索引擎支持32位IPv4（或128位IPv6）搜索密钥，每个具有关联的15位3级VPN标识值。

    Network packet latency measurement
    36.
    发明授权
    Network packet latency measurement 有权
    网络分组延迟测量

    公开(公告)号：US08792366B2

    公开(公告)日：2014-07-29

    申请号：US12916060

    申请日：2010-10-29

    Applicant: John Michael Terry ,  Wing Cheung ,  Surya Prakash Varanasi

    Inventor： John Michael Terry ,  Wing Cheung ,  Surya Prakash Varanasi

    IPC: H04L12/26

    CPC classification number: H04L43/0852 ,  H04L41/5009

    Abstract: A solution for network packet latency measurement includes, at a network device having a memory, storing a first time value indicating when an ingress port of the network device received a packet. The solution also includes storing a second time value indicating when an egress port of the network device received the packet for transmission towards another network device. The solution also includes storing a difference between the first time value and the second time value.

    Abstract translation: 用于网络分组等待时间测量的解决方案包括在具有存储器的网络设备处存储指示网络设备的入口端何时接收到分组的第一时间值。 解决方案还包括存储指示网络设备的出口何时接收到分组用于传输到另一网络设备的第二时间值。 解决方案还包括存储第一时间值和第二时间值之间的差异。

    Content Addressable Memory (CAM) Parity And Error Correction Code (ECC) Protection
    37.
    发明申请
    Content Addressable Memory (CAM) Parity And Error Correction Code (ECC) Protection 审中-公开
    内容可寻址内存（CAM）奇偶校验和纠错码（ECC）保护

    公开(公告)号：US20120110411A1

    公开(公告)日：2012-05-03

    申请号：US12916384

    申请日：2010-10-29

    Applicant: Wing Cheung ,  Joseph Juh-En Cheng ,  John Michael Terry

    Inventor： Wing Cheung ,  Joseph Juh-En Cheng ,  John Michael Terry

    IPC: G11C29/52 ,  H03M13/29 ,  H03M13/05 ,  G11C15/00 ,  G06F11/10

    CPC classification number: G06F11/1666 ,  G06F11/106 ,  G11C15/04 ,  G11C2029/0411 ,  H03M13/09

    Abstract: A memory system including a content addressable memory (CAM) array and a non-CAM array. The non-CAM array, which may share word lines with the CAM array, stores one or more error detection bits associated with each row of the CAM array. A state machine reads entries of the CAM array and corresponding error detection bits of the non-CAM array during idle cycles of the CAM array. Error detection logic identifies errors in the entries read from CAM array (using the retrieved error detection bits). If these errors are correctable, the error detection logic corrects the entry, and writes the corrected entry back to the CAM array (an updated set of error detection bits are also written to the non-CAM array). If these errors are not correctable, an interrupt is generated, which causes correct data to be retrieved from a shadow copy of the CAM array.

    Abstract translation: 一种包括内容寻址存储器（CAM）阵列和非CAM阵列的存储器系统。 可以与CAM阵列共享字线的非CAM阵列存储与CAM阵列的每一行相关联的一个或多个错误检测位。 在CAM阵列的空闲周期期间，状态机读取CAM阵列的条目和非CAM阵列的相应错误检测位。 错误检测逻辑识别从CAM阵列读取的条目中的错误（使用检索到的错误检测位）。 如果这些错误是可纠正的，则错误检测逻辑校正条目，并将修正的条目写回CAM阵列（更新的错误检测位组也写入非CAM阵列）。 如果这些错误不可纠正，则会产生一个中断，这会导致从CAM阵列的卷影副本中检索出正确的数据。

    NETWORK PACKET LATENCY MEASUREMENT
    38.
    发明申请
    NETWORK PACKET LATENCY MEASUREMENT 有权
    网络分组延迟测量

    公开(公告)号：US20120106365A1

    公开(公告)日：2012-05-03

    申请号：US12916060

    申请日：2010-10-29

    Applicant: John Michael Terry ,  Wing Cheung ,  Surya Prakash Varanasi

    Inventor： John Michael Terry ,  Wing Cheung ,  Surya Prakash Varanasi

    IPC: H04L12/26

    CPC classification number: H04L43/0852 ,  H04L41/5009

    Abstract: A solution for network packet latency measurement includes, at a network device having a memory, storing a first time value indicating when an ingress port of the network device received a packet. The solution also includes storing a second time value indicating when an egress port of the network device received the packet for transmission towards another network device. The solution also includes storing a difference between the first time value and the second time value.

    Abstract translation: 用于网络分组等待时间测量的解决方案包括在具有存储器的网络设备处存储指示网络设备的入口端何时接收到分组的第一时间值。 解决方案还包括存储指示网络设备的出口何时接收到分组用于传输到另一网络设备的第二时间值。 解决方案还包括存储第一时间值和第二时间值之间的差异。

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