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公开(公告)号：US20240021765A1
公开(公告)日：2024-01-18
申请号：US17414019
申请日：2021-06-04
Inventor： Jiyue SONG , Fei AI , Dewei SONG
CPC classification number: H01L33/62 , H01L33/0012 , G06V40/13 , H01L2933/0016 , H01L2933/0025 , H01L2933/0033
Abstract: In an array substrate of the present invention, only two insulating layers are arranged on a planarization layer. Compared with conventional techniques that require at least four insulating layers arranged on the planarization layer, a number of the insulating layers arranged on the planarization layer is reduced. Therefore, a number of photomasks is reduced in a manufacturing process of the array substrate, and the manufacturing process is simplified. The present invention also provides a manufacturing method of the array substrate, and a display panel.
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公开(公告)号：US20230309342A1
公开(公告)日：2023-09-28
申请号：US17771484
申请日：2022-04-13
Inventor： Hong CHENG , Yanqing GUAN , Chao TIAN , Fei AI , Guanghui LIU
CPC classification number: H01L27/3262 , G09G3/32 , H01L27/3265 , G09G2300/0426 , G09G2300/0842 , G09G2300/0861 , G09G2320/0233 , G09G2320/0242 , H01L27/1225
Abstract: A display panel, a pixel driving circuit, and a display device are provided. Driving transistors include a first transistor and a second transistor connected in parallel. An absolute value of a threshold voltage of the first transistor is greater than an absolute value of a threshold voltage of the second transistor. A carrier mobility of the first transistor is greater than a carrier mobility of the second transistor. A driving current is affected by characteristics of the second transistor and an increase speed is slowed down, which improves a problem of color unevenness of the display panel at low brightness.
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公开(公告)号：US20230176410A1
公开(公告)日：2023-06-08
申请号：US16963787
申请日：2020-06-23
Inventor： Dewei SONG , Fei AI
IPC: G02F1/1333 , G02F1/1368 , H01L27/12
CPC classification number: G02F1/133354 , G02F1/1368 , H01L27/1248
Abstract: The present application provides a display panel and a display device. The display panel includes an array substrate, a color filter substrate, and a colloid layer. The array substrate includes a thin film transistor layer and a passivation layer. The passivation layer includes at least one first connection element. The color filter substrate is disposed opposite to the array substrate. The colloid layer is arranged between the passivation layer and the color filter substrate, the colloid layer is connected to the first connection element, and the colloid layer and the first connection element couple the array substrate to the color filter substrate.
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公开(公告)号：US20230163136A1
公开(公告)日：2023-05-25
申请号：US16966119
申请日：2020-04-20
Inventor： Juncheng XIAO , Yong XU , Fei AI , Dewei SONG
IPC: H01L27/12
CPC classification number: H01L27/1225 , H01L27/1288 , H01L27/1285
Abstract: A display panel, an array substrate, and a manufacturing method thereof, wherein the array substrate includes a thin film transistor device, and an interface layer, a first transparent conductive layer, a passivation layer, and a second transparent conductive layer which are formed on the thin film transistor device in sequence. By replacing a planarization layer in the prior art with the interface layer, performing a gate re-etching process, and perforating the interface layer and the passivation layer to simultaneously form a deep via and a shallow via, a number of photomasks required to form the array substrate is reduced to 8. It effectively reduces costs of production materials and costs of photomasks.
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公开(公告)号：US20210408080A1
公开(公告)日：2021-12-30
申请号：US16757175
申请日：2019-12-12
Inventor： Fei AI , Dewei SONG
IPC: H01L27/12 , G02F1/1368 , G02F1/1343 , G02F1/136
Abstract: The invention provides a thin film transistor (TFT) array substrate, a manufacturing method thereof, and a display panel. The TFT array substrate includes a substrate. A buffer layer and a TFT functional layer are sequentially disposed on the substrate. The TFT functional layer includes an active layer (Active), a gate insulating layer (GI), a gate layer (GE), an interlayer insulating layer (ILD), and a source-drain layer (SD) that are sequentially disposed on the buffer layer. An inorganic insulating layer is disposed on the source-drain layer, and a backside indium tin oxide (BITO) layer, a passivation layer (PV), and a top indium tin oxide (TITO) layer are sequentially disposed on the inorganic insulating layer. The invention provides the TFT array substrate. The TFT array substrate adopts a new functional layer structure design, which can effectively reduce production cost and cycle time of the TFT array substrate.
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Patent Agency Ranking
公开(公告)号：US20250160143A1
公开(公告)日：2025-05-15
申请号：US17635074
申请日：2022-01-20
Inventor： Fei AI , Shiyu LONG
IPC: H10K59/131 , H10K59/12
Abstract: An array substrate and a display panel are disclosed. In the array substrate, a first metal layer includes a first connection segment and a second connection segment, or a second metal layer includes a first connection segment and a second connection segment. The array substrate further includes a first via hole defined above a sheltering-and-wiring metal layer and a second via hole defined above a shielding metal layer, and the first connection segment passes through the first via hole to connect with the sheltering-and-wiring metal layer and the second connection segment passes through the second via hole to connect with the shielding metal layer.
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公开(公告)号：US20250133826A1
公开(公告)日：2025-04-24
申请号：US17910800
申请日：2022-08-30
Inventor： Fei AI , Chengzhi LUO
IPC: H10D86/40
Abstract: The present disclosure provides a display panel and a mobile terminal, the display panel includes a substrate and a thin film transistor layer, the thin film transistor layer including a semiconductor layer, an insulating layer and a first metal layer, the insulating layer being disposed on the substrate and the semiconductor layer and covering the semiconductor layer, the first metal layer being disposed on the insulating layer, the insulating layer including at least one via hole, the first metal layer being connected to the semiconductor layer through the via hole, and an included angle between a sidewall of the via hole and a bottom surface of the insulating layer being greater than or equal to 85 degrees and less than or equal to 90 degrees.
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公开(公告)号：US20250089368A1
公开(公告)日：2025-03-13
申请号：US18567964
申请日：2023-09-26
Inventor： Huihui ZHAO , Chunpeng ZHANG , Fei AI , Jianfeng YUAN , Zhifu LI
IPC: H01L27/12 , H01L29/66 , H01L29/786
Abstract: A semiconductor device, a display panel, and a chip are provided in embodiments of the present application. The semiconductor device of the embodiments of the present application stacks a first conductor portion, a channel portion, and a second conductor portion to form a vertical active structure layer to realize a narrow channel. A growth direction of crystal grains arranged in the channel potion is consistent with a moving direction of carriers to provide a single crystal-like channel.
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公开(公告)号：US20250076722A1
公开(公告)日：2025-03-06
申请号：US18951716
申请日：2024-11-19
Inventor： Jiyue SONG , Fei AI
IPC: G02F1/1368 , G02F1/133 , H01L27/12
Abstract: A display panel includes an array substrate. The array substrate includes: a thin-film transistor (TFT) device, the TFT device including a first active pattern; and a photosensitive device, the photosensitive device including a first electrode, a second electrode, a connector electrode, and a second active pattern. The first electrode, the second electrode, the connector electrode, and the second active pattern constitute a vertical heterojunction structure.
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公开(公告)号：US20250072093A1
公开(公告)日：2025-02-27
申请号：US17925002
申请日：2022-11-07
Inventor： Zhifu LI , Guanghui LIU , Fei AI , Dewei SONG , Zhuang LI
IPC: H01L29/45 , H01L29/49 , H01L29/786
Abstract: A display panel is provided. The display panel includes a substrate and includes a first ohmic contact structure, a first boss, a second ohmic contact structure, a semiconductor structure, and a gate which are stacked on the substrate. The first boss includes at least one sidewall. By arranging the semiconductor structure on the sidewall of the first boss, a length of a channel can be shortened by using an existing technology, and a dimension of a thin film transistor can be reduced, so that an integration level of the thin film transistor in the display panel can be improved.
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