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公开(公告)号:US20240120451A1
公开(公告)日:2024-04-11
申请号:US18544727
申请日:2023-12-19
Applicant: InnoLux Corporation
Inventor: Jia-Yuan CHEN , Tsung-Han TSAI , Kuan-Feng LEE , Yuan-Lin WU
IPC: H01L33/58 , H01L25/075 , H01L27/15 , H01L31/14 , H01L31/16 , H01L33/00 , H01L33/44 , H01L33/48 , H01L33/62
CPC classification number: H01L33/58 , H01L25/0753 , H01L27/156 , H01L31/14 , H01L31/16 , H01L33/0012 , H01L33/005 , H01L33/0093 , H01L33/44 , H01L33/48 , H01L33/62
Abstract: An electronic assembly is provided. The electronic assembly includes a first circuit structure including a conductive structure, a second circuit structure disposed on the first circuit structure, a plurality of electronic elements disposed on the first circuit structure, and a connecting element disposed on the first circuit layer. The connecting element is disposed between two adjacent ones of the plurality electronic elements and electrically connected to the second circuit layer and one of the two adjacent ones of the plurality of electronic elements.
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公开(公告)号:US20240097066A1
公开(公告)日:2024-03-21
申请号:US18522890
申请日:2023-11-29
Applicant: Silanna UV Technologies Pte Ltd
Inventor: Petar Atanackovic
CPC classification number: H01L33/0012 , H01L33/06 , H01L33/325 , H01L33/508 , H01L33/60
Abstract: In some embodiments, a semiconductor structure includes a first conductivity type region comprising a first superlattice, and an i-type active region adjacent to the first conductivity type region comprising an i-type superlattice. The first conductivity type region can be a p-type region or an n-type region. The first superlattice can be comprised of a plurality of first unit cells comprising a first set of single crystal layers, and the i-type superlattice can be comprised of a plurality of i-type unit cells comprising a second set of single crystal layers. An average alloy content of the plurality of the first unit cells and the i-type unit cells can be constant along a growth direction. The structure can be configured such that electrons and holes recombine to generate a spectrum of light with a longest wavelength peak that corresponds to a transition between electron and hole confined energy states within the i-type superlattice.
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公开(公告)号:US20240021765A1
公开(公告)日:2024-01-18
申请号:US17414019
申请日:2021-06-04
Inventor: Jiyue SONG , Fei AI , Dewei SONG
CPC classification number: H01L33/62 , H01L33/0012 , G06V40/13 , H01L2933/0016 , H01L2933/0025 , H01L2933/0033
Abstract: In an array substrate of the present invention, only two insulating layers are arranged on a planarization layer. Compared with conventional techniques that require at least four insulating layers arranged on the planarization layer, a number of the insulating layers arranged on the planarization layer is reduced. Therefore, a number of photomasks is reduced in a manufacturing process of the array substrate, and the manufacturing process is simplified. The present invention also provides a manufacturing method of the array substrate, and a display panel.
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公开(公告)号:US20230307582A1
公开(公告)日:2023-09-28
申请号:US18020654
申请日:2021-10-14
Applicant: VERTILITE CO., LTD.
Inventor: Dong LIANG , Cheng ZHANG
CPC classification number: H01L33/382 , H01S5/4031 , H01L33/105 , H01L33/0041 , H01L33/0012 , H01S5/183
Abstract: Provided are a semiconductor light source and a driver circuit thereof. The semiconductor light source includes an active layer, a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, and a third electrode. The first semiconductor layer and the second semiconductor layer are located on two opposite sides of the active layer. The first electrode is in ohmic contact with the first semiconductor layer. The third electrode is in ohmic contact with the second semiconductor layer. A first dielectric layer is disposed between the first electrode and the second electrode. The first semiconductor layer is a p-type semiconductor layer, and the second semiconductor layer is an n-type semiconductor layer. Alternatively, the first semiconductor layer is an n-type semiconductor layer, and the second semiconductor layer is a p-type semiconductor layer.
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公开(公告)号:US20230238488A1
公开(公告)日:2023-07-27
申请号:US18118488
申请日:2023-03-07
Applicant: EPISTAR CORPORATION
Inventor: Chao-Hsing CHEN , Jia-Kuen WANG , Tzu-Yao TSENG , Tsung-Hsun CHIANG , Bo-Jiun HU , Wen-Hung CHUANG , Yu-Ling LIN
CPC classification number: H01L33/382 , H01L33/00 , H01L33/10 , H01L33/24 , H01L33/385 , H01L33/387 , H01L33/42 , H01L33/46 , H01L33/62 , H01L33/0012 , H01L33/02
Abstract: A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer and a second semiconductor layer; a first reflective layer formed on the first semiconductor layer and including a plurality of vias; a plurality of contact structures respectively filled in the vias and electrically connected to the first semiconductor layer; a second reflective layer including metal material formed on the first reflective layer and contacting the contact structures; a plurality of conductive vias surrounded by the semiconductor stack; a connecting layer formed in the conductive vias and electrically connected to the second semiconductor layer; a first pad portion electrically connected to the second semiconductor layer; and a second pad portion electrically connected to the first semiconductor layer, wherein a shortest distance between two of the conductive vias is larger than a shortest distance between the first pad portion and the second pad portion.
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公开(公告)号:US20190237624A1
公开(公告)日:2019-08-01
申请号:US16382873
申请日:2019-04-12
Applicant: EPISTAR CORPORATION
Inventor: Chao-Hsing CHEN , Yu-Chen YANG , Li-Ping JOU , Hui-Chun YEH , Yi-Wen KU
CPC classification number: H01L33/38 , H01L33/0012 , H01L33/08 , H01L33/20 , H01L33/30 , H01L33/382 , H01L33/44 , H01L33/46 , H01L33/60 , H01L33/62
Abstract: A light-emitting device comprises a semiconductor layer sequence comprising a first semiconductor layer having a first electrical conductivity, a second semiconductor layer having a second electrical conductivity, and an active layer interposed between the first semiconductor layer and the second semiconductor layer; a plurality of beveled trenches formed in the semiconductor layer sequence; a plurality of protruding structures respectively formed in the plurality of beveled trenches; a dielectric layer formed on the second semiconductor layer and an inner sidewall of the plurality of beveled trenches; a reflecting layer interposed between the semiconductor layer sequence and the dielectric layer; and a metal layer formed along the inner sidewall of the plurality of beveled trenches, wherein the dielectric layer, the reflecting layer and the metal layer are overlapping, the plurality of protruding structures and the reflecting layer are not overlapping.
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公开(公告)号:US20170263809A1
公开(公告)日:2017-09-14
申请号:US15594015
申请日:2017-05-12
Applicant: THE SILANNA GROUP PTY LTD
Inventor: Petar Atanackovic
IPC: H01L33/00 , H01L29/16 , H01L31/0304 , H01L33/34 , H01L31/105 , H01L31/18 , H01L33/12 , H01L33/32 , H01L33/06 , H01L31/0352
CPC classification number: H01L33/0075 , H01L29/1606 , H01L29/167 , H01L31/0288 , H01L31/03042 , H01L31/03044 , H01L31/03048 , H01L31/035263 , H01L31/105 , H01L31/1848 , H01L31/1856 , H01L33/0012 , H01L33/0079 , H01L33/06 , H01L33/12 , H01L33/325 , H01L33/343 , Y02E10/50
Abstract: A superlattice and method for forming that superlattice are disclosed. In particular, an engineered layered single crystal structure forming a superlattice is disclosed. The superlattice provides p-type or n-type conductivity, and comprises alternating host layers and impurity layers, wherein: the host layers consist essentially of a semiconductor material; and the impurity layers consist of a donor or acceptor material.
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公开(公告)号:US20170179328A1
公开(公告)日:2017-06-22
申请号:US15352921
申请日:2016-11-16
Applicant: International Business Machines Corporation
Inventor: Yann Astier , Huan Hu , Ning Li , Devendra K. Sadana , Joshua T. Smith , William T. Spratt
IPC: H01L31/173 , B01L3/00 , H01L31/0216 , H01L31/105 , H01L33/00
CPC classification number: H01L31/173 , B01L3/502715 , B01L3/502761 , B01L2200/0652 , B01L2200/10 , B01L2300/0627 , B01L2300/12 , G01N15/1436 , G01N15/1484 , G01N21/6428 , G01N33/54306 , G01N33/54373 , G01N2015/0065 , G01N2201/062 , H01L27/156 , H01L31/02164 , H01L31/035227 , H01L31/105 , H01L31/125 , H01L31/167 , H01L31/18 , H01L33/0012 , H01L33/18 , H01L33/20 , H01L33/58
Abstract: In one example, a device includes a trench formed in a substrate. The trench includes a first end and a second end that are non-collinear. A first plurality of semiconductor pillars is positioned near the first end of the trench and includes integrated light sources. A second plurality of semiconductor pillars is positioned near the second end of the trench and includes integrated photodetectors.
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公开(公告)号:US09653641B2
公开(公告)日:2017-05-16
申请号:US14757410
申请日:2015-12-23
Applicant: Seiko Epson Corporation
Inventor: Hiroki Nishioka
CPC classification number: H01L33/0045 , G03B21/005 , G03B21/2033 , H01L33/0012 , H01L33/10 , H01L33/14 , H01L33/36
Abstract: In a light emitting device, a light waveguide is provided with a first region including a central position, a second region including a first light emission surface, and a third region including a second light emission surface. A second cladding layer includes a plurality of noncontact regions. The plurality of noncontact regions intersect the light waveguide. A ratio of an area in which the plurality of noncontact regions overlap the first region to an area of the first region is greater than a ratio of an area in which the plurality of noncontact regions overlap the second region to an area of the second region, and is greater than a ratio of an area in which the plurality of noncontact regions overlap the third region to an area of the third region.
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公开(公告)号:US09614119B2
公开(公告)日:2017-04-04
申请号:US13976379
申请日:2011-12-29
Applicant: Yimin Kang , Han-Din Liu
Inventor: Yimin Kang , Han-Din Liu
IPC: H01L31/107 , H01L33/00 , H01L31/0352
CPC classification number: H01L33/0012 , H01L31/035272 , H01L31/1075
Abstract: An Si/Ge SACM avalanche photo-diodes (APD) having low breakdown voltage characteristics includes an absorption region and a multiplication region having various layers of particular thicknesses and doping concentrations. An optical waveguide can guide infrared and/or optical signals or energy into the absorption region. The resulting photo-generated carriers are swept into the i-Si layer and/or multiplication region for avalanche multiplication. The APD has a breakdown bias voltage of well less than 12 V and an operating bandwidth of greater than 10 GHz, and is therefore suitable for use in consumer electronic devices, high speed communication networks, and the like.
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