公开(公告)号：US09312187B2

公开(公告)日：2016-04-12

申请号：US13520791

申请日：2012-04-11

Applicant: Huaxiang Yin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/823807 ,  H01L29/7833 ,  H01L29/7843

Abstract: The present invention discloses a semiconductor device, comprising a first MOSFET; a second MOSFET; a first stress liner covering the first MOSFET and having a first stress; a second stress liner covering the second MOSFET and having a second stress; wherein the second stress liner and/or the first stress liner comprise(s) a metal oxide. In accordance with the high-stress CMOS and method of manufacturing the same of the present invention, a stress layer comprising a metal oxide is formed selectively on PMOS and NMOS respectively by using a CMOS compatible process, whereby carrier mobility of the channel region is effectively enhanced and the performance of the device is improved.

Abstract translation: 本发明公开了一种半导体器件，包括第一MOSFET; 第二个MOSFET; 覆盖所述第一MOSFET并具有第一应力的第一应力衬垫; 覆盖所述第二MOSFET并具有第二应力的第二应力衬垫; 其中所述第二应力衬垫和/或所述第一应力衬垫包括金属氧化物。 根据本发明的高应力CMOS及其制造方法，通过使用CMOS兼容工艺，分别在PMOS和NMOS上选择性地形成包含金属氧化物的应力层，由此，沟道区域的载流子迁移率有效地 增强了设备的性能，提高了设备​​性能。

公开(公告)号：US20150179797A1

公开(公告)日：2015-06-25

申请号：US14355664

申请日：2012-07-03

Applicant: Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/66636 ,  H01L29/7834

Abstract: The present invention discloses a semiconductor device, which comprises a substrate, a gate stack structure on the substrate, a channel region in the substrate under the gate stack structure, and source and drain regions at both sides of the channel region, wherein there is a stressed layer under and at both sides of the channel region, in which the source and drain regions are formed. According to the semiconductor device and the method for manufacturing the same of the present invention, a stressed layer is formed at both sides of and under the channel region made of a silicon-based material so as to act on the channel region, thereby effectively increasing the carrier mobility of the channel region and improving the device performance.

Abstract translation: 本发明公开了一种半导体器件，其包括衬底，衬底上的栅极堆叠结构，栅极堆叠结构下的衬底中的沟道区，以及沟道区两侧的源极和漏极区，其中存在 在形成源极和漏极区的沟道区的下侧和两侧具有应力层。 根据本发明的半导体器件及其制造方法，在由硅系材料制成的沟道区域的两侧和下方形成应力层，以作用于沟道区域，从而有效地增加 通道区域的载波移动性和设备性能的提高。

公开(公告)号：US20150115374A1

公开(公告)日：2015-04-30

申请号：US14387143

申请日：2012-04-26

Applicant: Huaxiang Yin ,  Xiaolong Ma ,  Changliang Qi ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Xiaolong Ma ,  Changliang Qi ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66575 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833

Abstract: The present invention provides a semiconductor structure comprising a substrate; a gate stack on the substrate; a spacer on the sidewalls of the gate stack; a source/drain junction extension formed in the substrate on both sides of the gate stack by epitaxial growth; and a source/drain region in the substrate on both sides of the source/drain junction extension. Accordingly, the present invention also provides methods for manufacturing the semiconductor structure. The present invention can provide a source/drain junction extension with a high doping concentration and a low junction depth, thereby effectively improving the performance of the semiconductor structure.

Abstract translation: 本发明提供一种包括基板的半导体结构; 衬底上的栅极堆叠; 在栅极堆叠的侧壁上的间隔物; 通过外延生长形成在栅极堆叠的两侧的衬底中的源极/漏极结延伸; 以及在源极/漏极结延伸部的两侧上的衬底中的源极/漏极区域。 因此，本发明还提供了制造半导体结构的方法。 本发明可以提供具有高掺杂浓度和低结深度的源极/漏极结延伸，从而有效地改善了半导体结构的性能。

公开(公告)号：US08921864B2

公开(公告)日：2014-12-30

申请号：US13380047

申请日：2011-11-09

Applicant: Xiaolong Ma ,  Hungjui Chen ,  Tsunglung Chang

Inventor： Xiaolong Ma ,  Hungjui Chen ,  Tsunglung Chang

IPC: H01L27/14 ,  G02F1/1343 ,  G02F1/1362 ,  H01L27/02 ,  H01L27/12

CPC classification number: G02F1/136259 ,  G02F1/136204 ,  G02F1/136286 ,  G02F2001/136263 ,  G02F2001/136272 ,  G02F2201/18 ,  G02F2201/40 ,  G02F2201/506 ,  H01L27/02 ,  H01L27/124

Abstract: The present invention provides a TFT-LCD array substrate having a gate-line metal layer, a data-line metal layer crossing the gate-line metal layer and a plurality of layers covering a periphery of the gate-line metal layer and the data-line metal layer; the gate-line metal layer has first gate lines and second gate lines parallel and alternately arranged, the date-line metal layer has first data lines and second data lines parallel and alternately arranged; the first gate line and the second gate line are electrically connected; the first data line and the second data line are electrically connected. The present invention further provides a manufacturing method of the TFT-LCD array substrate. Implementing the TFT-LCD array substrate and the manufacturing method can reduce the occurrence of line-broken in the active array of TFT-LCD, increase the aperture ratio of the product and enhance yield rate of the products.

Abstract translation: 本发明提供一种TFT-LCD阵列基板，其具有栅线金属层，与栅线金属层交叉的数据线金属层和覆盖栅极线金属层周边的多个层， 线金属层; 栅线金属层具有平行且交替布置的第一栅极线和第二栅极线，日期线金属层具有平行并交替布置的第一数据线和第二数据线; 第一栅极线和第二栅极线电连接; 第一数据线和第二数据线电连接。 本发明还提供了TFT-LCD阵列基板的制造方法。 实施TFT-LCD阵列基板及其制造方法可以减少TFT-LCD有源阵列中线路断裂的发生，提高产品的开口率，提高产品的产量。

公开(公告)号：US08912070B2

公开(公告)日：2014-12-16

申请号：US13812500

申请日：2012-10-12

Applicant: Xiaolong Ma ,  Huaxiang Yin ,  Zuozhen Fu

Inventor： Xiaolong Ma ,  Huaxiang Yin ,  Zuozhen Fu

IPC: H01L27/108

CPC classification number: H01L29/78 ,  H01L21/26506 ,  H01L29/0895 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/66356 ,  H01L29/66477 ,  H01L29/66659 ,  H01L29/7391 ,  H01L29/7835 ,  H01L29/7848

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stack structure on a substrate; forming a drain region in the substrate on one side of the gate stack structure; and forming a source region made of GeSn in the substrate on the other side of the gate stack structure; wherein the forming the source region made of GeSn comprises: implanting precursors in the substrate on the other side of the gate stack structure; and performing a laser rapid annealing such that the precursors react to produce GeSn alloy, thereby to constitute a source region; and wherein the step of implanting precursors further comprises: performing a pre-amorphization ion implantation, so as to form an amorphized region in the substrate; and implanting Sn in the amorphized region.

Abstract translation: 本发明公开了一种制造半导体器件的方法，包括：在衬底上形成栅叠层结构; 在所述栅极堆叠结构的一侧上的所述衬底中形成漏区; 以及在所述栅堆叠结构的另一侧的所述衬底中形成由GeSn制成的源区; 其中形成由GeSn制成的源极区域包括：在所述栅极堆叠结构的另一侧上的衬底中注入前体; 并进行激光快速退火，使得前体反应生成GeSn合金，从而构成源极区; 并且其中植入前体的步骤还包括：进行前非晶化离子注入，以在所述基底中形成非晶化区域; 并将Sn注入到非晶化区域中。