ROUTING NETS OVER CIRCUIT BLOCKS IN A HIERARCHICAL CIRCUIT DESIGN
    31.
    发明申请
    ROUTING NETS OVER CIRCUIT BLOCKS IN A HIERARCHICAL CIRCUIT DESIGN 有权
    在分层电路设计中通过电路块布线网络

    公开(公告)号:US20100325600A1

    公开(公告)日:2010-12-23

    申请号:US12490023

    申请日:2009-06-23

    CPC classification number: G06F17/5077

    Abstract: Some embodiments of the present invention provide a system that routes nets over circuit blocks in a hierarchical circuit design. During operation, the system can receive a set of circuit blocks. At least some terminals of the circuit blocks may be desired to be electrically linked together using a net which is expected to be routed over one or more circuit blocks. The system may divide an area associated with a block (e.g., an area in a metal layer which is situated above the block) into a set of tiles. Next, the system may assign costs to at least some of the tiles in the set of tiles. The system can then use the costs during routing. Note that using the costs of the tiles during routing makes it more likely that buffers can be used wherever required to meet slew and timing requirements.

    Abstract translation: 本发明的一些实施例提供一种在分层电路设计中将网络路由到电路块上的系统。 在运行期间,系统可以接收一组电路块。 电路块的至少一些端子可能期望使用期望在一个或多个电路块上布线的网电连接在一起。 系统可以将与块(例如,位于块之上的金属层中的区域)相关联的区域划分成一组瓦片。 接下来,系统可以将成本分配给该组瓦片中的至少一些瓦片。 然后,系统可以在路由期间使用成本。 请注意,在路由期间使用瓦片的成本使得缓冲区更有可能在需要满足压缩和时序要求的地方使用。

    METHODS, COMPUTER-READABLE MEDIA AND COMPUTER-IMPLEMENTED TOOLS FOR PRE-ROUTE REPEATER INSERTION
    32.
    发明申请
    METHODS, COMPUTER-READABLE MEDIA AND COMPUTER-IMPLEMENTED TOOLS FOR PRE-ROUTE REPEATER INSERTION 有权
    方法,计算机可读介质和计算机实现的前路由器插入工具

    公开(公告)号:US20100128760A1

    公开(公告)日:2010-05-27

    申请号:US12324439

    申请日:2008-11-26

    CPC classification number: G06F17/5077

    Abstract: A method of performing a pre-route repeater insertion methodology for at least part of a circuit design may include: partitioning at least part of a circuit design into a plurality of tiles; determining at least one attribute of individual tiles of the plurality of tiles; and determining a repeater solution based at least in part on the determined attributes of the individual tiles. A computer implemented tool for performing a pre-route repeater insertion methodology for at least part of a circuit design may include: a module configured to partition at least part of a circuit design into a plurality of tiles; a module configured to determine at least one attribute of individual tiles of the plurality of tiles; and a module configured to determine a repeater solution based at least in part on the determined attributes of the individual tiles.

    Abstract translation: 执行电路设计的至少一部分的前路由中继器插入方法的方法可以包括:将电路设计的至少一部分划分成多个瓦片; 确定所述多个瓦片中的各个瓦片的至少一个属性; 以及至少部分地基于所确定的各个瓦片的属性来确定中继器解决方案。 用于对电路设计的至少一部分执行预路由中继器插入方法的计算机实现工具可以包括:被配置为将电路设计的至少一部分划分成多个瓦片的模块; 模块,被配置为确定所述多个瓦片中的各个瓦片的至少一个属性; 以及模块,被配置为至少部分地基于所确定的各个瓦片的属性来确定中继器解决方案。

    Bandwidth Requests of Scheduling Services
    33.
    发明申请
    Bandwidth Requests of Scheduling Services 审中-公开
    调度服务的带宽请求

    公开(公告)号:US20090232160A1

    公开(公告)日:2009-09-17

    申请号:US12171170

    申请日:2008-07-10

    CPC classification number: H04W72/1284

    Abstract: Methods and apparatus for providing bandwidth requests of scheduling services, such as, for example, best effort services, in a telecommunication network are disclosed. An example method includes receiving a plurality of bandwidth requests from different scheduling connections. The example method further includes combining the plurality of bandwidth requests in a common bandwidth request.

    Abstract translation: 公开了用于在电信网络中提供调度服务的带宽请求(例如,尽力服务)的方法和装置。 示例性方法包括从不同的调度连接接收多个带宽请求。 该示例方法还包括在公共带宽请求中组合多个带宽请求。

    Timing driven pin assignment
    35.
    发明授权
    Timing driven pin assignment 有权
    定时驱动引脚分配

    公开(公告)号:US07577933B1

    公开(公告)日:2009-08-18

    申请号:US11601148

    申请日:2006-11-17

    CPC classification number: G06F17/5077

    Abstract: A mechanism is disclosed for determining pin assignments in an integrated circuit. More particularly, the mechanism involves accessing design information for the integrated circuit. The design information includes a floorplan that sets forth an arrangement of blocks in the integrated circuit and timing information for interconnections between the blocks. Based on the timing information, routing information is determined for the interconnections between the blocks. The routing information includes physical routes and physical pin placements for the interconnections.

    Abstract translation: 公开了用于确定集成电路中的引脚分配的机制。 更具体地,该机制涉及访问集成电路的设计信息。 设计信息包括阐述集成电路中的块的布置的布局图和用于块之间的互连的定时信息。 基于定时信息,确定块之间的互连的路由信息​​。 路由信息包括互连的物理路由和物理引脚放置。

    Converging repeater methodology for channel-limited SOC microprocessors
    36.
    发明授权
    Converging repeater methodology for channel-limited SOC microprocessors 有权
    用于通道限制SOC微处理器的汇聚中继器方法

    公开(公告)号:US07519933B2

    公开(公告)日:2009-04-14

    申请号:US11524820

    申请日:2006-09-21

    CPC classification number: G06F17/505

    Abstract: A method for inserting repeaters in an integrated circuit includes establishing a set of initial constraints for a given set of buses; assigning at least one repeater corresponding to each of the given set of buses based on the set of initial constraints; progressively relaxing the set of initial constraints to form a new set of constraints for a new set of buses and assigning at least one repeater corresponding to each of the new set of buses based on the new set of constraints; and routing assigned repeaters to each of the new set of buses in the integrated circuit.

    Abstract translation: 一种用于在集成电路中插入中继器的方法包括为给定的一组总线建立一组初始约束; 基于所述初始约束集,分配对应于所述给定总线集合中的每一个的至少一个中继器; 逐渐放松一组初始约束以形成新的一组总线的新的约束集合,并且基于新的约束集合分配对应于每组新的总线的至少一个中继器; 并将分配的中继器路由到集成电路中的每组新的总线。

    Converging repeater methodology for channel-limited SOC microprocessors
    37.
    发明申请
    Converging repeater methodology for channel-limited SOC microprocessors 有权
    用于通道限制SOC微处理器的汇聚中继器方法

    公开(公告)号:US20080077899A1

    公开(公告)日:2008-03-27

    申请号:US11524820

    申请日:2006-09-21

    CPC classification number: G06F17/505

    Abstract: A method for inserting repeaters in an integrated circuit includes establishing a set of initial constraints for a given set of buses; assigning at least one repeater corresponding to each of the given set of buses based on the set of initial constraints; progressively relaxing the set of initial constraints to form a new set of constraints for a new set of buses and assigning at least one repeater corresponding to each of the new set of buses based on the new set of constraints; and routing assigned repeaters to each of the new set of buses in the integrated circuit.

    Abstract translation: 一种用于在集成电路中插入中继器的方法包括为给定的一组总线建立一组初始约束; 基于所述初始约束集,分配对应于所述给定总线集合中的每一个的至少一个中继器; 逐渐放松一组初始约束以形成新的一组总线的新的约束集合,并且基于新的约束集合分配对应于每组新的总线的至少一个中继器; 并将分配的中继器路由到集成电路中的每组新的总线。

    COMMUNICATION SYSTEM
    38.
    发明申请
    COMMUNICATION SYSTEM 有权
    通讯系统

    公开(公告)号:US20070286077A1

    公开(公告)日:2007-12-13

    申请号:US11740810

    申请日:2007-04-26

    Applicant: Yi Wu

    Inventor: Yi Wu

    CPC classification number: H04L1/1835 H04L1/1854

    Abstract: A method of transmitting data in a communication system. Data packets are transmitted from a first node to a second node on a first channel. An acknowledgement packet is transmitted from the second node to the first node on a second channel in response to receiving a number of packets on the first channel. The number of data packets that the acknowledgment packet is sent in response to is adjustable.

    Abstract translation: 一种在通信系统中发送数据的方法。 数据分组在第一信道上从第一节点发送到第二节点。 响应于在第一信道上接收到多个分组,确认分组从第二节点发送到第二信道上的第一节点。 响应中发送确认数据包的数据包数量是可调整的。

    Methods and devices for detecting and isolating serial bus faults
    39.
    发明申请
    Methods and devices for detecting and isolating serial bus faults 审中-公开
    用于检测和隔离串行总线故障的方法和设备

    公开(公告)号:US20070043981A1

    公开(公告)日:2007-02-22

    申请号:US11297533

    申请日:2005-12-07

    Inventor: Yi Wu Yi Chen Sen Chan

    CPC classification number: G06F11/0793 G06F11/0745 G06F11/221

    Abstract: A method for detecting and isolating serial bus faults. Whether any bus fault has occurred on a serial bus coupled to a device through an isolator is detected. When a bus fault occurs on the serial bus, the isolator is controlled to isolate the device from the serial bus. Whether the device fails is then determined. When the device does not fail, the isolator is controlled to couple the device to the serial bus. When the device fails, an alert is issued, and the isolation of the devicecontinues.

    Abstract translation: 一种检测和隔离串行总线故障的方法。 检测到通过隔离器耦合到设备的串行总线上是否发生任何总线故障。 当串行总线发生总线故障时,隔离器被控制以将设备与串行总线隔离。 然后确定设备是否失败。 当设备没有故障时,隔离器被控制以将设备耦合到串行总线。 当设备发生故障时,会发出警报,并且发送设备的隔离。

    Megasonic cleaner and dryer system
    40.
    发明授权
    Megasonic cleaner and dryer system 有权
    超声波清洗机和烘干机系统

    公开(公告)号:US06928751B2

    公开(公告)日:2005-08-16

    申请号:US10171430

    申请日:2002-06-12

    CPC classification number: H01L21/67051 H01L21/67034 Y10S134/902

    Abstract: An apparatus includes a rotatable chuck for supporting a substrate and a splash guard. The splash guard surrounds the chuck and surrounds a substrate mounted on the chuck. The splash guard has a portion that deflects fluid being flung off the substrate by centrifugal action in a manner so as to not splash back onto the substrate. The splash guard is moveable between a process position in which the upper annular edge of the splash guard extends above the chuck and a substrate on the chuck, and a load/unload position in which the splash guard is tilted so that one side of the upper annular edge is below an upper edge of the chuck. The movement of the splash guard facilitates loading and unloading of a substrate.

    Abstract translation: 一种装置包括用于支撑衬底和防溅罩的可旋转卡盘。 防溅罩围绕卡盘并围绕安装在卡盘上的基板。 防溅罩具有通过离心作用将流体从基板上偏离的部分,以便不会溅回到基板上。 防溅罩可以在其中防溅罩的上部环形边缘在卡盘上方延伸到卡盘上的基板和加载/卸载位置之间移动,在该位置,防溅罩倾斜使得防护罩的上侧 环形边缘在卡盘的上边缘下方。 防溅罩的运动有助于衬底的装载和卸载。

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