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    Layered chip package and method of manufacturing same
    31.
    发明申请
    Layered chip package and method of manufacturing same 有权
    分层芯片封装及其制造方法

    公开(公告)号：US20100044879A1

    公开(公告)日：2010-02-25

    申请号：US12222955

    申请日：2008-08-20

    申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Tatsuya Harada ,  Nobuyuki Okuzawa ,  Satoru Sueki ,  Hiroshi Ikejima

    发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Tatsuya Harada ,  Nobuyuki Okuzawa ,  Satoru Sueki ,  Hiroshi Ikejima

    IPC分类号： H01L23/52 ,  H01L21/00

    CPC分类号： H01L25/0657 ,  G11C16/102 ,  H01L24/01 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06596 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. The plurality of layer portions include at least one layer portion of a first type and at least one layer portion of a second type. The layer portions of the first and second types each include a semiconductor chip. The layer portion of the first type further includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the layer portion of the second type does not include any electrode connected to the semiconductor chip and having an end face located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end face of each of the plurality of electrodes.

    摘要翻译： 层状芯片封装包括具有多个层部分的主体和布置在主体的侧表面上的布线。 多个层部分包括第一类型的至少一个层部分和第二类型的至少一个层部分。 第一和第二类型的层部分都包括半导体芯片。 第一类型的层部分还包括多个电极，每个电极连接到半导体芯片，并且每个电极具有位于布置有布线的主体的侧表面的端面，而第二类型的层部分 不包括连接到半导体芯片并且具有位于布置有布线的主体的侧表面的端面的任何电极。 布线连接到多个电极中的每一个的端面。