公开(公告)号：US20050170578A1

公开(公告)日：2005-08-04

申请号：US10772520

申请日：2004-02-04

申请人： Chia-Shun Hsiao ,  Chunchieh Huang ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel Wang

发明人： Chia-Shun Hsiao ,  Chunchieh Huang ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel Wang

IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11539 ,  H01L27/115 ,  H01L27/11526

摘要： Nonvolatile memory wordlines (160) are formed as sidewall spacers on sidewalls of control gate structures (280). Each control gate structure may contain floating and control gates (120, 140), or some other elements. Pedestals (340) are formed adjacent to the control gate structures before the conductive layer (160) for the wordlines is deposited. The pedestals will facilitate formation of the contact openings (330.1) that will be etched in an overlying dielectric (310) to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.

摘要翻译： 非易失性存储器字线（160）形成为控制栅极结构（280）的侧壁上的侧壁间隔物。 每个控制栅极结构可以包含浮动和控制栅极（120,140）或一些其它元件。 在用于字线的导电层（160）被沉积之前，基座（340）形成为与控制栅极结构相邻。 基座将有助于形成将在上覆电介质（310）中蚀刻的接触开口（330.1），以形成与字线的接触。 基座可以是虚拟结构。 基座可以物理接触两个字线。

公开(公告)号：US20050054174A1

公开(公告)日：2005-03-10

申请号：US10655705

申请日：2003-09-05

申请人： Chia-Shun Hsiao ,  Dong Kim

发明人： Chia-Shun Hsiao ,  Dong Kim

IPC分类号： H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/31111 ,  H01L21/823481 ,  H01L29/42368

摘要： A method and structure are provided with reduced gate wrap around to advantageously control for threshold voltage and increase stability in semiconductor devices. A spacer is provided aligned to field dielectric layers to protect the dielectric layers during subsequent etch processes. The spacer is then removed prior to subsequently forming a part of a gate oxide layer and a gate conductor layer. Advantageously, the spacer protects the corner area o the field dielectric and also allows for enhanced thickness of the gate oxide near the corners.

摘要翻译： 提供了一种方法和结构，其具有减少的栅极环绕，以有利地控制阈值电压并增加半导体器件的稳定性。 提供与场介电层对准的间隔物，以在随后的蚀刻工艺期间保护电介质层。 然后在随后形成栅极氧化物层和栅极导体层的一部分之前移除间隔物。 有利地，间隔物保护场电介质的角区域，并且还允许靠近拐角的栅极氧化物的增强的厚度。

公开(公告)号：US06864148B1

公开(公告)日：2005-03-08

申请号：US10655705

申请日：2003-09-05

申请人： Chia-Shun Hsiao ,  Dong Jun Kim

发明人： Chia-Shun Hsiao ,  Dong Jun Kim

IPC分类号： H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/76 ,  H01L21/31 ,  H01L21/3205

CPC分类号： H01L21/76232 ,  H01L21/31111 ,  H01L21/823481 ,  H01L29/42368

摘要： A method and structure are provided with reduced gate wrap around to advantageously control for threshold voltage and increase stability in semiconductor devices. A spacer is provided aligned to field dielectric layers to protect the dielectric layers during subsequent etch processes. The spacer is then removed prior to subsequently forming a part of a gate oxide layer and a gate conductor layer. Advantageously, the spacer protects the corner area o the field dielectric and also allows for enhanced thickness of the gate oxide near the corners.

公开(公告)号：US20050037530A1

公开(公告)日：2005-02-17

申请号：US10658934

申请日：2003-09-09

申请人： Chia-Shun Hsiao

发明人： Chia-Shun Hsiao

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L21/00

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/66825

摘要： Dielectric regions (210) are formed on a semiconductor substrate between active areas of nonvolatile memory cells. The top portions of the dielectric region sidewalls are etched to recess the top portions laterally away from the active areas. Then a conductive layer is deposited to form the floating gates (410). The recessed portions of the dielectric sidewalls allow the floating gates to be wider at the top. The gate coupling ratio is increased as a result. Other features are also provided.

摘要翻译： 电介质区域（210）形成在非易失性存储单元的有源区域之间的半导体衬底上。 蚀刻电介质区域侧壁的顶部以将顶部部分横向远离有源区域。 然后沉积导电层以形成浮栅（410）。 电介质侧壁的凹陷部分允许浮动栅极在顶部较宽。 结果，门耦合比增大。 还提供其他功能。

公开(公告)号：US06566196B1

公开(公告)日：2003-05-20

申请号：US10146979

申请日：2002-05-15

申请人： Barbara Haselden ,  Chia-Shun Hsiao ,  Chunchieh Huang ,  Jin-Ho Kim ,  Chung Wai Leung ,  Kuei-Chang Tsai

发明人： Barbara Haselden ,  Chia-Shun Hsiao ,  Chunchieh Huang ,  Jin-Ho Kim ,  Chung Wai Leung ,  Kuei-Chang Tsai

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  Y10S438/954

摘要： In a nonvolatile memory, a floating gate (124) is covered with ONO (98), and a control gate polysilicon layer (124) is formed on the ONO. After the control gate is patterned, the control gate sidewalls are oxidized to form a protective layer (101) of silicon dioxide. This oxide protects the control gate polysilicon during a subsequent etch of the silicon nitride portion (98.2) of the ONO. Therefore, the silicon nitride can be removed with an isotropic etch. A potential damage to the substrate isolation dielectric (210) is therefore reduced. Other embodiments are also provided.

摘要翻译： 在非易失性存储器中，浮动栅极（124）被ONO（98）覆盖，并且在ONO上形成控制栅多晶硅层（124）。 在控制栅极被图案化之后，控制栅极侧壁被氧化以形成二氧化硅的保护层（101）。 该氧化物在ONO的氮化硅部分（98.2）的随后蚀刻期间保护控制栅极多晶硅。 因此，可以用各向同性蚀刻去除氮化硅。 因此，减小了对衬底隔离电介质（210）的潜在损害。 还提供了其他实施例。

公开(公告)号：US06391705B1

公开(公告)日：2002-05-21

申请号：US09547481

申请日：2000-04-12

申请人： Chia-Shun Hsiao ,  Chao-chueh Wu ,  Chih-yu Lee

发明人： Chia-Shun Hsiao ,  Chao-chueh Wu ,  Chih-yu Lee

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10876 ,  H01L27/10891

摘要： A high density semiconductor memory device is provided. The memory device includes a transistor and a capacitor formed along the sidewall of a trench. The trench is formed below the crossing of a word line and a bit line. The capacitor is formed by diffusing dopants into the substrate surrounding the lower portion of the trench, depositing an insulating layer, and depositing a conducting layer into the trench. The transistor is formed in the substrate adjacent to the upper sidewall of the trench. The source region is formed by thermal drive-in, and the drain region is formed by ion-implantation. The gate electrode is formed by depositing a conducting material into the trench. A gate contact window connects the gate electrode to the word line, and a drain contact window connects the drain to the bit line. The drain region of two adjacent memory cells are connected, and share the same drain contact window. An isolation layer surrounds the common drain region and the two transistors sharing a drain contact window to prevent signal interference with other transistors.

摘要翻译： 提供了一种高密度半导体存储器件。 存储器件包括沿沟槽的侧壁形成的晶体管和电容器。 沟槽形成在字线和位线的交叉点下方。 电容器通过将掺杂剂扩散到围绕沟槽下部的衬底中，沉积绝缘层，并将导电层沉积到沟槽中而形成。 晶体管形成在与沟槽的上侧壁相邻的衬底中。 源极区域由热驱动形成，漏极区域通过离子注入形成。 栅极通过将导电材料沉积到沟槽中而形成。 栅极接触窗将栅电极连接到字线，漏极接触窗将漏极连接到位线。 两个相邻的存储单元的漏极区域被连接，并且共享相同的漏极接触窗口。 隔离层围绕公共漏极区域，并且两个晶体管共享漏极接触窗口以防止与其它晶体管的信号干扰。

公开(公告)号：US06291286B1

公开(公告)日：2001-09-18

申请号：US09200912

申请日：1998-11-27

申请人： Chia-Shun Hsiao

发明人： Chia-Shun Hsiao

IPC分类号： H01L218234

CPC分类号： H01L27/10867

摘要： A method of fabricating deep trench capacitors of high density Dynamic Random Access Memory (DRAM) cells is disclosed: first, providing a semiconductor substrate, and then forming a trench on the semiconductor substrate; sequentially forming a capacitor dielectric layer, a first polysilicon storage node, dielectric collars and a second polysilicon stud inside the trench; performing two-step ion implantation to form shallow and deep strap regions on one side of the trench; forming a third polysilicon layer and an isolation layer overlaying the dielectric collars and second polysilicon stud inside the trench to complete a buried strap formation; and forming an access field effect transistor on the semiconductor substrate.

摘要翻译： 公开了制造高密度动态随机存取存储器（DRAM）单元的深沟槽电容器的方法：首先，提供半导体衬底，然后在半导体衬底上形成沟槽; 在沟槽内顺序地形成电容器电介质层，第一多晶硅存储节点，介电环和第二多晶硅柱; 执行两步离子注入以在沟槽的一侧上形成浅和深的带区域; 形成第三多晶硅层和覆盖所述沟槽内的所述介质环和第二多晶硅柱的隔离层，以完成掩埋带形成; 以及在所述半导体衬底上形成存取场效应晶体管。