Error correction by symbol reconstruction in binary and multi-valued cyclic codes
    32.
    发明授权
    Error correction by symbol reconstruction in binary and multi-valued cyclic codes 有权
    通过二进制和多值循环码中的符号重构进行纠错

    公开(公告)号:US09203438B2

    公开(公告)日:2015-12-01

    申请号:US11739189

    申请日:2007-04-24

    申请人: Peter Lablans

    发明人: Peter Lablans

    摘要: Methods, apparatus and systems for error correction of n-valued symbols in codewords of p n-valued symbols with n>2 and for n=2 and k information symbols have been disclosed. Coders and decoders using a Linear Feedback Shift Registers (LFSR) are applied to generate codewords and detect the presence of errors. An LFSR can be in Fibonacci or Galois configuration. Errors can be corrected by execution of an n-valued expression in a deterministic non-iterative way. Deterministic error correction methods based on known symbols in error are provided. Corrected codewords can be identified by comparison with received codewords in error. N-valued LFSR based pseudo-noise generators and methods to determine if an LFSR is appropriate for generating error correcting codes are also disclosed. Methods and apparatus applying error free assumed windows and error assumed windows are disclosed. Systems using the error correcting methods, including communication systems and data storage systems are also provided.

    摘要翻译: 已经公开了用于对具有n≥2且n = 2的k个p个符号的码字中的n值符号进行纠错的方法,装置和系统以及k个信息符号。 应用使用线性反馈移位寄存器(LFSR)的编码器和解码器来生成码字并检测错误的存在。 LFSR可以是斐波那契或伽罗瓦配置。 可以通过以确定性的非迭代方式执行n值表达式来纠正错误。 提供了基于已知错误符号的确定性纠错方法。 可以通过与错误的接收码字进行比较来识别校正的码字。 还公开了基于N值的基于LFSR的伪噪声发生器以及用于确定LFSR是否适于产生纠错码的方法。 公开了应用无误假定窗口和错误假设窗口的方法和装置。 还提供了使用纠错方法的系统,包括通信系统和数据存储系统。

    Data encryption and decryption with a key by an N-state inverter modified switching function
    33.
    发明授权
    Data encryption and decryption with a key by an N-state inverter modified switching function 失效
    数据加密和解密由一个N状态的逆变器修改了切换功能

    公开(公告)号:US08149143B2

    公开(公告)日:2012-04-03

    申请号:US13083763

    申请日:2011-04-11

    申请人: Peter Lablans

    发明人: Peter Lablans

    IPC分类号: H03M7/00

    CPC分类号: G06F7/503

    摘要: Methods and apparatus for implementing an n-state ripple-adder scheme coder with n≧2 using an n-state reversible switching function and a non-reversible n-state switching function acting upon a first and a second word of at least 2 n-state symbols are disclosed. Corresponding decoding methods and apparatus are also disclosed. A resulting codeword may be a codeword which can be decoded by using the identical or different n-state switching functions in a corresponding ripple adder scheme decoder. Feistel networks and LFSRs apply the coding and decoding. Systems using the coding and decoding methods may be communication, storage and/or financial systems.

    摘要翻译: 使用n状态可逆切换功能实现n≥2的n状态波纹加法器方案编码器的方法和装置,以及作用于至少2n的第一和第二字的不可逆n状态切换功能, 状态符号被公开。 还公开了相应的解码方法和装置。 所产生的码字可以是可以通过在对应的纹波加法器解码器中使用相同或不同的n状态切换功能来解码的码字。 Feistel网络和LFSR应用编码和解码。 使用编码和解码方法的系统可以是通信,存储和/或金融系统。

    Ternary and Multi-Value Digital Signal Scramblers, Decramblers and Sequence Generators
    34.
    发明申请
    Ternary and Multi-Value Digital Signal Scramblers, Decramblers and Sequence Generators 有权
    三元和多值数字信号扰频器,解扰器和序列发生器

    公开(公告)号:US20110170697A1

    公开(公告)日:2011-07-14

    申请号:US13027387

    申请日:2011-02-15

    申请人: Peter Lablans

    发明人: Peter Lablans

    IPC分类号: H04K1/00

    CPC分类号: H03K19/20

    摘要: Reversible and self reversing multi-value scrambling functions created by applying multi-value inverters are disclosed. The generation of possible multi-value inverters is also presented. Corresponding multi-value descrambling functions are also disclosed. The multi-value functions are used in circuits that scramble and descramble multi-value signals. The multi-value functions can also be used in signal generators. Such signal generators do not require the use of multipliers. The auto-correlation of the signals generated by the signal generators is also presented. Electronic circuits that implement the multi-value functions are also described.

    摘要翻译: 公开了通过应用多值逆变器创建的可逆和自反转的多值加扰功能。 还提出了可能的多值逆变器的产生。 还公开了相应的多值解扰功能。 多值函数用于加扰和解扰多值信号的电路中。 多值函数也可用于信号发生器。 这样的信号发生器不需要使用乘法器。 还提出了由信号发生器产生的信号的自相关。 还描述了实现多值功能的电子电路。

    Methods and Apparatus in Alternate Finite Field Based Coders and Decoders
    35.
    发明申请
    Methods and Apparatus in Alternate Finite Field Based Coders and Decoders 审中-公开
    基于有限域的编码和解码器的方法和装置

    公开(公告)号:US20110064214A1

    公开(公告)日:2011-03-17

    申请号:US12952482

    申请日:2010-11-23

    申请人: Peter Lablans

    发明人: Peter Lablans

    IPC分类号: H04L9/28

    摘要: Methods and apparatus for coding and decoding n-state symbols with n≧2 and n>2 and n>3 and n>4 are provided wherein at least one implementation of an addition over an alternate finite field GF(n) and an inverter defined by a multiplication over the alternate finite field GF(n) are provided. Encoders and decoders implementing a single n-state truth table that is a truth table of an addition over an alternate finite field GF(n) modified in accordance with at least one inverter defined by a multiplication over the alternate finite field GF(n) are also provided. Encoders include scramblers, Linear Feedback Shift Register (LFSR) based encoders, sequence generator based encoders, block coders, streaming cipher encoders, transposition encoders, hopping rule encoders, Feistel network based encoders, check symbol based encoders, Hamming coder, error correcting encoders, encipherment encoders, Elliptic Curve Coding encoders and all corresponding decoders. Systems applying encoders and decoders also are provided.

    摘要翻译: 提供了用于编码和解码具有n≥2和n≥2且n> 3和n≥4的n状态符号的方法和装置,其中至少一个在替代有限域GF(n)和反相器上的加法的实现被定义 通过交替有限域GF(n)上的乘法。 实现单个n态真值表的编码器和解码器是根据通过交替有限域GF(n)上的乘法定义的至少一个反相器修改的替代有限域GF(n)的加法的真值表, 也提供。 编码器包括加扰器,基于线性反馈移位寄存器(LFSR)的编码器,基于序列发生器的编码器,块编码器,流密码编码器,转置编码器,跳频规则编码器,基于Feistel网络的编码器,基于校验符号的编码器,汉明编码器,纠错编码器, 加密编码器,椭圆曲线编码编码器和所有相应的解码器。 还提供了应用编码器和解码器的系统。

    Multi-state latches from n-state reversible inverters

    公开(公告)号:US07782089B2

    公开(公告)日:2010-08-24

    申请号:US12635307

    申请日:2009-12-10

    申请人: Peter Lablans

    发明人: Peter Lablans

    IPC分类号: H03K19/00

    摘要: N-valued re-circulating latches using n-valued reversible inverters with n>3 are disclosed. Latches using n-valued self-reversing inverters are provided; latches using n-valued universal inverters are provided; and latches using inverters which are not self-reversing or universal are also provided. A latch may use two individually controlled gates. It may also use one individually controlled gate. N-valued latches are provided wherein a state is represented by a signal being an independent instance of a physical phenomenon. A latch not using absence-of-signal as a state is also provided.

    Generation and Self-Synchronizing Detection of Sequences Using Addressable Memories
    37.
    发明申请
    Generation and Self-Synchronizing Detection of Sequences Using Addressable Memories 审中-公开
    使用可寻址记忆的序列的生成和自同步检测

    公开(公告)号:US20100180097A1

    公开(公告)日:2010-07-15

    申请号:US12730690

    申请日:2010-03-24

    申请人: Peter Lablans

    发明人: Peter Lablans

    IPC分类号: G06F12/06

    摘要: Methods and apparatus to implement LFSRs and LFSR based sequence generators, detectors, scramblers and descramblers by addressable memory are disclosed. The methods and apparatus may be processing binary or n-valued symbols, with n>2. Methods to uniquely characterize n-valued Gold sequence are also disclosed. Self-synchronizing methods to detect sequences which can be decomposed into unique words are also disclosed. Methods and apparatus to implement Fibonacci and Galois LFSRs are disclosed.

    摘要翻译: 公开了通过可寻址存储器来实现基于LFSR和LFSR的序列发生器,检测器,扰频器和解扰器的方法和装置。 方法和装置可以处理二进制或n值符号,其中n> 2。 还公开了唯一表征n值Gold序列的方法。 还公开了用于检测可分解为独特词的序列的自同步方法。 公开了实施斐波那契和伽罗瓦LFSR的方法和装置。

    Implementing Logic Functions With Non-Magnitude Based Physical Phenomena
    38.
    发明申请
    Implementing Logic Functions With Non-Magnitude Based Physical Phenomena 审中-公开
    实现基于非幅度物理现象的逻辑函数

    公开(公告)号:US20100164548A1

    公开(公告)日:2010-07-01

    申请号:US12710809

    申请日:2010-02-23

    申请人: Peter Lablans

    发明人: Peter Lablans

    IPC分类号: H03K19/20

    CPC分类号: H03K19/20

    摘要: An n-valued switch with n≧2 and n>2 and n>7, with an input enabled to receive a signal in one of n states, an output enabled to provide a signal in one of at least 2 states, under control of a control signal having one of at least 2 states is disclosed. Signals are instances of a physical phenomenon, an instance representing a state. N-valued inverters are also disclosed. Different types of signals are disclosed, including optical signals with different wavelengths, electrical signals with different frequencies and signals represented by a presence of a material. A kit including an n-valued switch is also disclosed.

    摘要翻译: 具有n≥2且n> 2且n> 7的n值开关,其输入使能以在n个状态之一中接收信号,该输出使得能够在至少2个状态之一提供信号,在...的控制下 公开了具有至少2个状态之一的控制信号。 信号是物理现象的实例,表示状态的实例。 还公开了N值逆变器。 公开了不同类型的信号,包括具有不同波长的光信号,具有不同频率的电信号和由材料的存在表示的信号。 还公开了包括n值开关的套件。

    Multi-Value Digital Calculating Circuits, Including Multipliers
    39.
    发明申请
    Multi-Value Digital Calculating Circuits, Including Multipliers 有权
    多值数字计算电路,包括乘数

    公开(公告)号:US20090234900A1

    公开(公告)日:2009-09-17

    申请号:US12472731

    申请日:2009-05-27

    申请人: Peter Lablans

    发明人: Peter Lablans

    CPC分类号: G06F7/49

    摘要: Apparatus and method for performing multi-value arithmetic operations are disclosed. Multi-value signals can be added, subtracted and multiplied using a first truth table to generate a residue and a second truth table to generate a carry. Additionally, method and apparatus to efficiently perform the function a0b1+a1b0 on multi-value signals are disclosed. Also an efficient method of processing large binary signals is disclosed.

    摘要翻译: 公开了用于执行多值算术运算的装置和方法。 可以使用第一个真值表来添加,减去和乘以多值信号以生成残差和第二个真值表以生成进位。 另外,公开了在多值信号上有效执行功能a0b1 + a1b0的方法和装置。 还公开了一种处理大二进制信号的有效方法。

    Multi-value digital calculating circuits, including multipliers
    40.
    发明授权
    Multi-value digital calculating circuits, including multipliers 失效
    多值数字计算电路,包括乘法器

    公开(公告)号:US07562106B2

    公开(公告)日:2009-07-14

    申请号:US11018956

    申请日:2004-12-20

    申请人: Peter Lablans

    发明人: Peter Lablans

    IPC分类号: G06F15/00 G06F7/52

    CPC分类号: G06F7/49

    摘要: Apparatus and method for performing multi-value arithmetic operations are disclosed. Multi-value signals can be added, subtracted and multiplied using a first truth table to generate a residue and a second truth table to generate a carry. Additionally, method and apparatus to efficiently perform the function a0b1+a1b0 on multi-value signals are disclosed. Also an efficient method of processing large binary signals is disclosed.

    摘要翻译: 公开了用于执行多值算术运算的装置和方法。 可以使用第一个真值表来添加,减去和乘以多值信号以生成残差和第二个真值表以生成进位。 另外,公开了在多值信号上有效执行功能a0b1 + a1b0的方法和装置。 还公开了一种处理大二进制信号的有效方法。