公开(公告)号：US10714448B2

公开(公告)日：2020-07-14

申请号：US16203635

申请日：2018-11-29

申请人： Unimicron Technology Corp.

发明人： Chin-Sheng Wang ,  Ra-Min Tain

IPC分类号： H01L23/00 ,  H01L23/498

摘要： A chip module includes a body, a bump, and a first bonding layer. The bump is disposed on the body. The first bonding layer is disposed on the bump. The first bonding layers and the bump are made of the same conductive material and the first bonding layer is porous.

公开(公告)号：US10673194B2

公开(公告)日：2020-06-02

申请号：US16055160

申请日：2018-08-06

申请人： Unimicron Technology Corp.

发明人： Yu-Hsiang Chuang ,  Guodong Li ,  He Lei ,  Jianyu Zhang

IPC分类号： H01R43/00 ,  H01R12/55

摘要： A manufacturing method of connector structure including the following steps is provided. First, providing a dielectric layer having. Then, forming a first adhesive layer and a second adhesive layer on two opposite sides of the dielectric layer respectively. Then, providing at least one first conductive elastic cantilever and at least one second conductive elastic cantilever, wherein the first conductive elastic cantilever comprises a first fixing end portion and a first free end portion, and the second conductive elastic cantilever comprises a second fixing end portion and a second free end portion. Then, fixing the first fixing end portion and the second fixing end portion to the first adhesive layer and the second adhesive layer respectively, wherein the first fixing end portion is aligned with the second fixing end portion. Afterward, forming at least one conductive via for electrically connecting the first conductive elastic cantilever with the second conductive elastic cantilever.

公开(公告)号：US20200163215A1

公开(公告)日：2020-05-21

申请号：US16221587

申请日：2018-12-17

申请人： Unimicron Technology Corp.

发明人： Wen-Liang Yeh ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Cheng-Hui Wu

IPC分类号： H05K1/11 ,  H05K1/03 ,  H05K3/28 ,  H05K3/00

摘要： A carrier structure including a glass substrate, a buffer layer, and an inner circuit layer is provided. The glass substrate has a first surface, a second surface opposite to the first surface, and at least one through hole penetrating through the glass substrate. The buffer layer is disposed on the first surface and the second surface of the glass substrate. The inner circuit layer is disposed on the buffer layer and in the through hole of the glass substrate. The inner circuit layer exposes a part of the buffer layer.

公开(公告)号：US20200075711A1

公开(公告)日：2020-03-05

申请号：US16159726

申请日：2018-10-15

申请人： Unimicron Technology Corp.

发明人： Yu-Hua Chen ,  Fu-Yang Chen ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Wei-Ti Lin

IPC分类号： H01L49/02 ,  H01L23/522 ,  H01L23/532 ,  H01L23/15 ,  H01L23/498

摘要： A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure. A substrate structure obtained by the manufacturing method of the substrate structure is provided.

公开(公告)号：US20200043839A1

公开(公告)日：2020-02-06

申请号：US16167540

申请日：2018-10-23

申请人： Unimicron Technology Corp.

发明人： Cheng-Ta Ko ,  Kai-Ming Yang ,  Yu-Hua Chen ,  Tzyy-Jang Tseng

IPC分类号： H01L23/498

摘要： A package substrate structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The vias and the pads are disposed on the first substrate, and fills in the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar is disposed between the first substrate and the second substrate, where each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills in the gaps between the conductive pillars. A bonding method of the package substrate structure is also provided.

公开(公告)号：US20190296102A1

公开(公告)日：2019-09-26

申请号：US16145130

申请日：2018-09-27

申请人： Unimicron Technology Corp.

发明人： Ra-Min Tain ,  Chen-Hua Cheng ,  Chin-Sheng Wang ,  Chung-Chi Huang

IPC分类号： H01L49/02 ,  H01L23/522

摘要： An embedded component structure including a circuit board, an electronic component, a dielectric layer and a connection circuit layer and a manufacturing method thereof is provided. The circuit board has a through hole and includes a core layer, a first circuit layer, and a second circuit layer. The first circuit layer and the second circuit layer are disposed on the core layer. The through hole penetrates the first circuit layer and the core layer. The electronic component including a plurality of connection pads is disposed within the through hole where the dielectric layer is filled in. The connection circuit layer covers and contacts a first electrical connection surface of the first circuit layer and at least one of a second electrical connection surface of each of the connection pads.

公开(公告)号：US20190250502A1

公开(公告)日：2019-08-15

申请号：US16395244

申请日：2019-04-26

申请人： Unimicron Technology Corp.

发明人： Pu-Ju Lin ,  Shih-Lian Cheng ,  Yu-Hua Chen ,  Cheng-Ta Ko ,  Jui-Jung Chien ,  Wei-Tse Ho

IPC分类号： G03F1/50 ,  G03F7/20 ,  H05K3/42 ,  H05K3/18 ,  H05K3/12 ,  H05K3/10 ,  H05K3/00 ,  G01K15/00 ,  G01K7/24 ,  H05K3/24 ,  H05K3/06

CPC分类号： G03F1/50 ,  G01K7/24 ,  G01K15/007 ,  G03F7/2032 ,  G03F7/2047 ,  H05K3/0023 ,  H05K3/064 ,  H05K3/107 ,  H05K3/1275 ,  H05K3/182 ,  H05K3/241 ,  H05K3/422 ,  Y10T29/49124

摘要： A mask structure and a manufacturing method of the mask structure are provided. The mask structure includes a transparent substrate, a patterned metal layer, and a plurality of microlens structures. The patterned metal layer is disposed on the transparent substrate and exposing a portion of the transparent substrate. The microlens structures are disposed on the transparent substrate exposed by a portion of the patterned metal layer and being in contact with the portion of the patterned metal layer.

公开(公告)号：US10324370B2

公开(公告)日：2019-06-18

申请号：US15256757

申请日：2016-09-06

申请人： Unimicron Technology Corp.

发明人： Pu-Ju Lin ,  Shih-Lian Cheng ,  Yu-Hua Chen ,  Cheng-Ta Ko ,  Jui-Jung Chien ,  Wei-Tse Ho

IPC分类号： H05K3/00 ,  G03F1/50 ,  H05K3/06 ,  H05K3/24 ,  G01K7/24 ,  G01K15/00 ,  H05K3/10 ,  H05K3/12 ,  H05K3/18 ,  H05K3/42 ,  G03F7/20

摘要： A manufacturing method of a circuit substrate is provided. A substrate is provided. A positive photoresist layer is coated on the substrate. Once exposure process is performed on the positive photoresist layer disposed on the substrate so as to simultaneously form concaves with at least two different depths.

公开(公告)号：US10271433B2

公开(公告)日：2019-04-23

申请号：US14855404

申请日：2015-09-16

申请人： Unimicron Technology Corp.

发明人： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen ,  Shih-Lian Cheng

IPC分类号： H05K3/30 ,  H05K3/00 ,  H05K1/18 ,  H01L23/538 ,  H01L23/00 ,  H05K3/06 ,  H05K3/42 ,  H05K3/46

摘要： A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is formed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed.

公开(公告)号：US20190088401A1

公开(公告)日：2019-03-21

申请号：US15818773

申请日：2017-11-21

申请人： Unimicron Technology Corp.

发明人： Chang-Fu Chen ,  Chun-Hao Chen ,  Kuan-Hsi Wu ,  Pi-Te Pan

IPC分类号： H01F27/28 ,  H01F27/24 ,  H05K1/16 ,  H05K1/11

摘要： A carrier structure includes a substrate, a first patterned circuit layer and at least one magnetic element. The substrate has a first surface and an opening passing through the substrate. The first patterned circuit layer is disposed on the first surface of the substrate and includes an annular circuit for generating an electromagnetic field. The magnetic element is disposed within the opening of the substrate, wherein the magnetic element couples the annular circuit and acts in response to the magnetic force of the electromagnetic field.