Method and apparatus for creating and executing integrated executables in a heterogeneous architecture
    31.
    发明授权
    Method and apparatus for creating and executing integrated executables in a heterogeneous architecture 有权
    用于在异构架构中创建和执行集成可执行文件的方法和装置

    公开(公告)号:US07243333B2

    公开(公告)日:2007-07-10

    申请号:US10280244

    申请日:2002-10-24

    IPC分类号: G06F9/44 G06F9/30

    CPC分类号: G06F8/451

    摘要: The present invention provides a compilation system for compiling and linking an integrated executable adapted to execute on a heterogeneous parallel processor architecture. The compiler and linker compile different segments of the source code for a first and second processor architecture, and generate appropriate stub functions directed at loading code and data to remote nodes so as to cause them to perform operations described by the transmitted code on the data. The compiler and linker generate stub objects to represent remote execution capability, and stub objects encapsulate the transfers necessary to execute code in such environment.

    摘要翻译: 本发明提供了一种用于编译和链接适用于在异构并行处理器架构上执行的集成可执行程序的编译系统。 编译器和链接器为第一和第二处理器架构编译源代码的不同段,并且生成针对加载代码和数据到远程节点的适当的存根功能,以使它们执行由传输的代码对数据描述的操作。 编译器和链接器生成存根对象以表示远程执行能力,并且存根对象封装了在这种环境中执行代码所需的传输。

    Processor network
    32.
    发明申请
    Processor network 审中-公开
    处理器网络

    公开(公告)号:US20070044064A1

    公开(公告)日:2007-02-22

    申请号:US10546615

    申请日:2004-02-19

    IPC分类号: G06F17/50

    CPC分类号: G06F9/5066 G06F8/451

    摘要: Processes are automatically allocated to processors in a processor array, and corresponding communications resources are assigned at compile time, using information provided by the programmer. The processing tasks in the array are therefore allocated in such a way that the resources required to communicate data between the different processors are guaranteed.

    摘要翻译: 过程被自动分配给处理器阵列中的处理器,并且使用编程器提供的信息在编译时分配对应的通信资源。 因此,阵列中的处理任务被分配成使得在不同处理器之间传送数据所需的资源得到保证。

    Method and apparatus for accelerating processing of a non-sequential instruction stream on a processor with multiple compute units
    33.
    发明申请
    Method and apparatus for accelerating processing of a non-sequential instruction stream on a processor with multiple compute units 有权
    用于加速具有多个计算单元的处理器上的非顺序指令流的处理的方法和装置

    公开(公告)号:US20060174236A1

    公开(公告)日:2006-08-03

    申请号:US11045888

    申请日:2005-01-28

    IPC分类号: G06F9/45

    CPC分类号: G06F8/451

    摘要: Accelerating processing of a non-sequential instruction stream on a processor with multiple compute units by broadcasting to a plurality of compute units a generic instruction stream derived from a sequence of instructions; the generic instruction stream including an index section and a compute section; applying the index section to localized data stored in each compute unit to select one of a plurality of stored local parameter sets; and applying in each compute unit the selected set of parameters to the local data according to the compute section to produce each compute unit's localized solution to the generic instruction.

    摘要翻译: 通过向多个计算单元广播从指令序列导出的通用指令流来加速处理具有多个计算单元的处理器上的非顺序指令流; 所述通用指令流包括索引部分和计算部分; 将索引部分应用于存储在每个计算单元中的本地化数据,以选择多个存储的本地参数集中的一个; 以及根据计算部分在每个计算单元中将选定的参数集合应用于本地数据,以产生每个计算单元对通用指令的本地化解决方案。

    Processor allocating method/apparatus in multiprocessor system, and medium for storing processor allocating program
    34.
    发明授权
    Processor allocating method/apparatus in multiprocessor system, and medium for storing processor allocating program 失效
    多处理器系统中的处理器分配方法/装置,以及用于存储处理器分配程序的介质

    公开(公告)号:US06199093B1

    公开(公告)日:2001-03-06

    申请号:US08683417

    申请日:1996-07-18

    申请人: Yuji Yokoya

    发明人: Yuji Yokoya

    IPC分类号: G06F900

    CPC分类号: G06F8/451

    摘要: In a processor allocating apparatus employed in a multiprocessor system capable of executing a plurality of tasks in a parallel manner, a compiler compiles a source program of a program constructed of parallel tasks to produce a target program 3, and also to produce a communication amount table for tasks, which holds therein a data amount of communication process operations executed among the respective tasks of the parallel tasks. While referring to both the communication amount table for tasks, and a processor communication cost table for defining data communication time per unit data in sets of all processors employed in the scheduler makes a decision such that a processor where communication time among the tasks becomes minimum is allocated to the task of the parallel tasks, and registers this decision to a processor management table.

    摘要翻译: 在能够以并行方式执行多个任务的多处理器系统中使用的处理器分配装置中,编译器编译由并行任务构成的程序的源程序以产生目标程序3,并且还产生通信量表 其中保存有并行任务的各个任务之间执行的通信处理操作的数据量的任务。 同时参考任务的通信量表和用于定义在调度器中采用的所有处理器的集合中的每单位数据的数据通信时间的处理器通信费用表进行决定,使得任务之间的通信时间变得最小的处理器是 分配给并行任务的任务,并将该决定注册到处理器管理表。

    Self-scheduling parallel computer system and method
    35.
    发明授权
    Self-scheduling parallel computer system and method 失效
    自调并行计算机系统及方法

    公开(公告)号:US5408658A

    公开(公告)日:1995-04-18

    申请号:US730365

    申请日:1991-07-15

    IPC分类号: G06F9/38 G06F9/45 G06F15/16

    摘要: An incremental method is described for distributing the instructions of an execution sequence among a plurality of processing elements for execution in parallel. The distribution is based upon anticipated availability times of the needed input values for each instruction as well as the anticipated availability times of each processing element for handling each instruction. A self-parallelizing computer system and method are also described for asynchronously processing the distributed instructions in two modes of execution on a set of processing elements which communicate with each other.

    摘要翻译: 描述了用于在多个处理元件之间并行执行执行序列的指令的分发方法。 该分配基于每个指令的所需输入值的预期可用时间以及用于处理每个指令的每个处理元件的预期可用时间。 还描述了一种自并行计算机系统和方法,用于在一组彼此通信的处理元件上以两种执行模式异步处理分布式指令。

    Hierarchical scheduling method for processing tasks having precedence
constraints on a parallel processing system
    36.
    发明授权
    Hierarchical scheduling method for processing tasks having precedence constraints on a parallel processing system 失效
    用于处理在并行处理系统上具有优先约束的任务的分级调度方法

    公开(公告)号:US5392430A

    公开(公告)日:1995-02-21

    申请号:US968717

    申请日:1992-10-30

    CPC分类号: G06F8/451 Y10S707/99933

    摘要: A plurality of queries (jobs) which consist of sets of tasks with precedence constraints between them are optimally scheduled in two stages of scheduling for processing on a parallel processing system. In a first stage of scheduling, multiple optimum schedules are created for each job, one optimum schedule for each possible number of processors which might be used to execute each job, and an estimated job execution time is determined for each of the optimum schedules created for each job, thereby producing a set of estimated job execution times for each job which are a function of the number of processors used for the job execution. Precedence constraints between tasks in each job are respected in creating all of these optimum schedules. Any known optimum scheduling method for parallel processing tasks that have precedence constraints among tasks may be used but a novel preferred method is also disclosed. The second stage of scheduling utilizes the estimated job execution times determined in the first stage of scheduling to create an overall optimum schedule for the jobs. The second stage of scheduling does not involve precedence constraints because the precedence constraints are between tasks within the same job and not between tasks in separate jobs, so jobs may be scheduled without observing any precedence constraints. Any known optimum scheduling method for the parallel processing of jobs that have no precedence constraints may be used, but a novel preferred method is also disclosed.

    摘要翻译: 由并行处理系统处理的调度的两个阶段最佳地调度由它们之间的优先约束的任务组组成的多个查询(作业)。 在第一阶段的调度中,为每个作业创建多个最优时间表,为可能用于执行每个作业的每个可能数量的处理器提供一个最佳时间表,并且为每个作业执行的每个最佳时间表确定估计的作业执行时间 每个作业,从而为作业执行的处理器数量的函数产生一组每个作业的估计作业执行时间。 在创建所有这些最佳时间表时尊重每个作业中任务之间的优先约束。 可以使用在任务之间具有优先约束的并行处理任务的任何已知的最佳调度方法,但是也公开了一种新颖的优选方法。 第二阶段调度利用在调度的第一阶段确定的估计作业执行时间来创建作业的总体最佳调度。 调度的第二阶段不涉及优先约束,因为优先约束位于同一作业中的任务之间,而不是在单独作业中的任务之间,因此可以调度作业而不观察任何优先约束。 可以使用用于并行处理没有优先约束的作业的任何已知的最佳调度方法,但是也公开了一种新颖的优选方法。

    Multiprocessor computer system with dynamic allocation of
multiprocessing tasks and processor for use in such multiprocessor
computer system
    38.
    发明授权
    Multiprocessor computer system with dynamic allocation of multiprocessing tasks and processor for use in such multiprocessor computer system 失效
    多处理器计算机系统具有动态分配的多处理任务和处理器,用于这种多处理器计算机系统

    公开(公告)号:US4459664A

    公开(公告)日:1984-07-10

    申请号:US351397

    申请日:1982-02-23

    CPC分类号: G06F8/451

    摘要: A multiprogramming data processing system comprises a plurality of data processing devices P1, P2, P3, P4 each having local storage 110-116 and has furthermore an interconnecting standard bus 100. The program is divided in program segments S1-S4, while the program segments are grouped into program portions (k, m, n). The respective program portions are each stored at one of the local memory sections. When an extended branch instruction calls an address in a different program portion, a portion change interrupt signal (26) is generated, whereby dynamical allocation of the execution of program segments may be realized. When a privileged portion (0) is called, the portion change interrupt is nullified, both at the calling to, (28) and the return (23) from the privileged program portion.

    摘要翻译: 多重编程数据处理系统包括多个数据处理装置P1,P2,P3,P4,每个数据处理装置具有本地存储器110-116,并且还具有互连标准总线100.该程序被划分为程序段S1-S4,而程序段 被分组为程序部分(k,m,n)。 各个程序部分各自存储在本地存储器部分之一中。 当扩展分支指令调用不同程序部分中的地址时,产生部分改变中断信号(26),由此可以实现程序段的执行的动态分配。 当调用特权部分(0)时,部分更改中断在从特权程序部分调用到(28)和返回(23)时无效。