摘要:
A programmable data processor or controller serving as the main control in a control system contains an executive program for controlling the transfer of information between the processor and system equipment, updating that information during on-line control of the equipment and modifying the executive program to change operating parameters of the system while the data processor is controlling the system equipment. Modification of the executive program and displaying of system parameters relative to the executive program and the system equipment is accomplished through the use of an operator's console which communicates with the data processor and system equipment as a result of operator intervention.
摘要:
An instruction execution modification mechanism is described for a digital data processor wherein multiple programs or tasks are performed in a concurrent manner by means of a time slice mechanism which causes the instructions from the different programs to be executed in an interleaved manner. Instructions from the different programs are executed during different successive time slice intervals. The instruction execution modification mechanism is responsive to the occurrences of various predetermined conditions in the data processing system for selectively modifying the normal execution of different ones of the instructions in different ones of the programs. To this end, there is provided a program list mechanism listing the modifiable programs, an instruction list mechanism listing the modifiable instructions and a modification storage mechanism for storing modification signals for the different instructions. If, during a given time slice interval, the program to be executed is on the modifiable program list and the instruction to be executed is on the modifiable instruction list and the appropriate condition is occurring in the data processing system, then the modification storage mechanism is enabled to send the modification signals for this instruction to the instruction execution unit for modifying the normal execution of this instruction.
摘要:
In an information processing system of the type having widely dispersed terminals tied together by a series communications link, common data which is of interest to all stations is collected and registered in a simplified manner. The common information, consisting of the status of each of the stations, is collected by any station sending out a search instruction as part of an information word. As the information word passes through each successive station, each respective station adds a status bit to the information word indicating the status thereof. When the new-completed information word returns to the originating station, the common data is registered and displayed. Also the common data is sent, along with a "register common data" instruction, to all other stations via the communication link. Upon receipt of such information and instruction, each station registers and displays the common data.
摘要:
An execution system for instructions having source and sink operand designations includes an arithmetic unit, execution means for holding an instruction for controlling the arithmetic unit and a plurality of operand registers, each having tag means associated therewith for indicating the nature of data stored therein. Instruction modification logic, on the basis of indications of availability of the operand registers, inserts modified source and sink operand register designations in instructions which are then stored in an instruction register stack. Interlock logic controls the transfer of instructions from the instruction register stack to the execution means as a function of the source and sink operand register designations in the modified instructions and the data tags associated with the operand registers.
摘要:
A data communication system which includes a data distributor, a communication station and a plurality of front-end-processors. These front-end-processors are connected with a computer through a common bus. The distributor distributes the data received by the station to one available front-end-processor, which preprocesses the received data, and transfers the pre-processed data to the computer through the bus. By operating the front-end-processors in parallel with respect to successively received packets of data, the processing speed of the system is increased.
摘要:
An arrangement for introducing modifications in the program of a program-controlled system. Each time a modified version of a selected program function is stored in the system, it is tagged with a function sequence number; meanwhile, the original version of the program function is retained in the system. Each time a program process is initiated, it is tagged with a process sequence number. The two types of sequence numbers are assigned from a common source. Whenever the selected program function is called by a program process, a comparison is made between the process sequence number and the function sequence number. If the comparison indicates that the process was initiated before the modification was stored in the system, the original version of the selected program function is executed; otherwise, the modified version is executed. Thus, the original version or the modified version is used consistently throughout the active life of a process.
摘要:
A multifunction routing network. The routing network is provided with a function control means including a condition responsive logic network having an iterative multifunction control loop. Register and memory means are also provided in the routing network which are operatively associated with the control means for providing input conditions thereto and for receiving output conditions therefrom. The logic network is provided with a multistable means having a plurality of states and is responsive to the states thereof and the input conditions thereto to provide a plurality of control functions of both a data control and an execute non-data control nature for the routing network. A computer, an input keyboard, an audio-visual playback device, and a television are also provided which are operatively associated with the register and memory means for providing input conditions thereto and for responding to output conditions therefrom.
摘要:
Apparatus and method for determining how a computer program is performing by sampling the operative conditions of a number of operating elements of a computer, such as the elements of the processing unit and the memory thereof. The information obtained from such sampling can be used to establish whether the program is ''''waiting,'''' ''''executing'''' or ''''actively computing.'''' Thus, a review of this information can be used to determine if the computer is being adequately utilized by the program and, if not, how it can be more efficiently utilized. The information is extracted randomly during the execution of the program following which the information is categorized and read out so as to be in an observable form.
摘要:
The invention relates to a programming panel which preferably comprises a micro-processor and whereby an operator can generate or modify the contents of steps of a user program by means of a number of selection means and value input means, inter alia on the basis of indications displayed on display means for this purpose. The user program is at the disposal of a machine control system, it preferably being possible to couple the programming panel to the system by way of a bus connection. The programming panel comprises standard selection means, notably for so-termed movement primitives.
摘要:
A microprogrammed pipeline data processing unit includes a first control store, a second control store and a plurality of hardware sequence control circuits. The first control store includes a plurality of storage locations, each location for storing an address field and a control sequence field for each program instruction required to be executed by the processing unit. The second control store includes a plurality of groups of storage locations, each group storing microinstructions required for executing at least a portion of at least one program instruction. Each sequence includes at least one microinstruction which contains a restart field coded to specify the conditions under which the hardware sequence circuits continue instruction execution. For each program instruction which can not be executed by the plurality of hardware sequence circuits in a pipeline mode, the control sequence field is coded to include a predetermined bit pattern. When decoded, the hardware sequence circuits is conditioned to enter an escape state enabling control to be transferred to a sequence specified by the address field. Instruction execution proceeds under microprogram control while the hardware sequence circuits remain in the same state. Upon the decoding of a microinstruction containing a restart field, the hardware sequence circuits are switched from the escape state to a state which enables the continuing of hardware instruction execution in a pipeline mode.