公开(公告)号：US5500947A

公开(公告)日：1996-03-19

申请号：US269991

申请日：1994-07-01

Applicant: George M. Uhler ,  John F. Brown, III

Inventor： George M. Uhler ,  John F. Brown, III

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/34 ,  G06F9/24

CPC classification number: G06F9/34 ,  G06F9/22 ,  G06F9/3016

Abstract: A method of specifying the operands for a microcoded CPU employs a combination of a set of microinstruction routines for generic operand modes, along with hardware primitives for selecting various specific types of operand treatment. Decoding of a machine-level instruction produces an entry point for the microstore, selecting one of the set of generic operand modes. Also, decoding of the instruction produces control bits that are used directly to select the specific operand type or used by the hardware primitives. In this way, branching is avoided in the microinstruction sequences used for operand specifying, but yet the amount of microcode needed is a minimum.

Abstract translation: 指定微编码CPU的操作数的方法采用一组用于通用操作数模式的微指令例程的组合，以及用于选择各种特定类型的操作数处理的硬件原语。 机器级指令的解码产生微型存储器的入口点，选择一组通用操作数模式之一。 此外，指令的解码产生直接用于选择特定操作数类型或由硬件基元使用的控制位。 以这种方式，在用于操作数指定的微指令序列中避免了分支，但是所需的微代码量是最小的。

公开(公告)号：US4747044A

公开(公告)日：1988-05-24

申请号：US643512

申请日：1984-08-23

Applicant: Carson T. Schmidt ,  Chenyu Chao ,  Gregory D. Brinson ,  Jerrold L. Allen ,  Barry L. Loges ,  Timothy G. Goldsbury ,  Robert O. Gunderson ,  Jerry K. Herreweyers

Inventor： Carson T. Schmidt ,  Chenyu Chao ,  Gregory D. Brinson ,  Jerrold L. Allen ,  Barry L. Loges ,  Timothy G. Goldsbury ,  Robert O. Gunderson ,  Jerry K. Herreweyers

IPC: G06F9/22 ,  G06F12/10 ,  G06F13/08

CPC classification number: G06F9/22 ,  G06F12/1063

Abstract: A data processing system including an addressable main memory for storing data and directly executable microinstructions, and a central processing chip having a data interface terminal and an instruction terminal. A processor memory bus is connected between the main addressable memory and the central processing chip data interface terminal. An instruction bus is connected between the central processing chip instruction terminal and the addressable memory.The directly executable microinstructions in the addressable main memory are fetched from the main memory by an apparatus which includes an instruction address circuit connected to the processor memory bus and the instruction bus. The instruction address circuit includes a virtual address register circuit for receiving a portion of a virtual address from the instruction bus, and a portion of the mentioned virtual address from the processor memory bus. A virtual-to-real translation circuit in the instruction address circuit translates the virtual address in the virtual address register to a real address in the addressable memory from which an executable microinstruction may be fetched.

Abstract translation: 一种数据处理系统，包括用于存储数据和可直接执行的微指令的可寻址主存储器，以及具有数据接口终端和指令终端的中央处理芯片。 处理器存储器总线连接在主可寻址存储器和中央处理芯片数据接口终端之间。 指令总线连接在中央处理芯片指令终端和可寻址存储器之间。 可寻址主存储器中的可直接执行的微指令通过包括连接到处理器存储器总线和指令总线的指令地址电路的装置从主存储器中取出。 指令地址电路包括用于从指令总线接收虚拟地址的一部分的虚拟地址寄存器电路和来自处理器存储器总线的所述虚拟地址的一部分。 指令地址电路中的虚拟到实际的转换电路将虚拟地址寄存器中的虚拟地址转换为可寻址存储器中的可实际地址，可从中获取可执行的微指令。

公开(公告)号：US3831148A

公开(公告)日：1974-08-20

申请号：US32004873

申请日：1973-01-02

Applicant: HONEYWELL INF SYSTEMS

Inventor： GREENWALD D ,  HOLTEY T

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/32 ,  G06F11/10 ,  G06F11/22 ,  G06F11/267 ,  G11C29/16 ,  G06F11/04

CPC classification number: G06F11/2236 ,  G06F9/22 ,  G06F11/10 ,  G11C29/16

Abstract: Diagnostic apparatus tests the operation of a control store included within data processing apparatus to verify the contents of each storage location and the operation of logic circuits associated therewith. The diagnostic apparatus is utilized when a resident maintenance routine stored within the control store is referenced which causes the read out of a microinstruction included within a predetermined control store location. Logic circuits included within the diagnostic apparatus decode the microinstruction and generate a subcommand which transfers control to the diagnostic apparatus. The diagnostic apparatus inhibits all operations except the addressing and the reading of the control store locations. The contents of the control store locations are checked in sequence by checking circuits until either the logic circuits decode a second microinstruction or until an error is detected. When the checking circuits detect an error, they cause the diagnostic apparatus to halt the test. At this time, the contents of the control store address register are displayed indicating where the failure occurred. When no failures are displayed, testing continues until a second microinstruction is decoded by the apparatus which completes the testing by causing the transfer of control back to the control store enabling execution of subsequently read microinstructions.

Abstract translation: 诊断装置测试包括在数据处理装置内的控制存储器的操作，以验证每个存储位置的内容和与其相关联的逻辑电路的操作。 当存储在控制存储器内的驻留维护程序被参考时，利用诊断装置，这导致包含在预定控制存储位置内的微指令的读出。 包括在诊断装置内的逻辑电路解码微指令并产生将控制传送到诊断装置的子命令。 诊断装置禁止除控制存储位置的寻址和读取之外的所有操作。 通过检查电路来顺序地检查控制存储位置的内容，直到逻辑电路解码第二微指令或直到检测到错误为止。 当检查电路检测到错误时，它们使诊断装置停止测试。 此时，显示控制存储地址寄存器的内容，指示发生故障的位置。 当没有显示故障时，测试继续进行，直到由完成测试的设备对第二微指令进行解码，通过使控制转移回控制存储器，从而能够执行随后读取的微指令。

公开(公告)号：US3728690A

公开(公告)日：1973-04-17

申请号：US3728690D

申请日：1971-08-26

Applicant: HONEYWELL INF SYSTEMS

Inventor： HOLTEY T ,  GREENWALD D

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/32 ,  G06F9/38 ,  G06F11/277 ,  G06F11/28 ,  G06F11/04

CPC classification number: G06F9/3869 ,  G06F9/22 ,  G06F9/226 ,  G06F9/268 ,  G06F11/277

Abstract: Diagnostic hardware and a method for diagnosis and confidence testing of ROM branching capabilities. Logical circuitry including an RIT flip-flop, which when set modifies the operation of a halt ''''HLT'''' micro-op which normally stops the clock, so that the halt ''''HLT'''' micro-op will not stop the clock and its absence or the presence of any other micro-op will stop the clock. Execution of any of a predetermined set of branch microinstructions to predetermined memory locations, sets the RIT flip-flop and causes a branch to a location containing a ''''HLT.'''' If branching operates properly, the program continues; if not the machine halts, thus identifying the error and avoiding loss of control of the machine.

Abstract translation: 诊断硬件和ROM分支功能的诊断和置信度测试方法。 包括RIT触发器的逻辑电路，当设置修改暂停“HLT”微操作的操作时，通常停止时钟，使得停止“HLT”微操作不会停止时钟及其不存在或不存在 任何其他微操作的存在将停止时钟。 对预定的存储器位置执行预定的一组分支微指令中的任何一个，设置RIT触发器并使分支到包含“HLT”的位置。 如果分支运作正常，程序继续; 如果不是机器停止，从而识别错误并避免机器的失控。

公开(公告)号：US3696340A

公开(公告)日：1972-10-03

申请号：US3696340D

申请日：1970-11-09

Applicant: TOKYO SHIBAURA ELECTRIC CO

Inventor： MATSUSHITA SHIGENORI ,  SATO FUMITAKA ,  MIURA HARUHISA

IPC: G06F9/22 ,  G06F11/267 ,  G06F9/16

CPC classification number: G06F11/2236 ,  G06F9/22

Abstract: A microprogram execution control for fault diagnosis includes a first and a second address register. The first address register designates the microaddress of one microstep stored in a fixed memory which is designated by a diagnostic microprogram information succeeding a diagnostic program instruction from a main memory. After one microstep is executed, the first address register designates a specified microaddress in the fixed memory, and the second address register stores the microaddress of a next microstep to be executed. At a step during the succeeding diagnostic routine, the content of the second address register is stored into the main memory.

Abstract translation: 用于故障诊断的微程序执行控制包括第一和第二地址寄存器。 第一地址寄存器指定存储在固定存储器中的一个微步的微地址，其由来自主存储器的诊断程序指令之后的诊断微程序信息指定。 在执行一个微步骤之后，第一地址寄存器指定固定存储器中的指定微地址，并且第二地址寄存器存储要执行的下一微步的微地址。 在接下来的诊断程序中的步骤中，将第二地址寄存器的内容存储到主存储器中。

公开(公告)号：US3245044A

公开(公告)日：1966-04-05

申请号：US15273061

申请日：1961-11-16

Applicant: IBM

Inventor： MEADE ROBERT M ,  CONROY EUGENE D

IPC: G06F9/22 ,  G06F9/42

CPC classification number: G06F9/4426 ,  G06F9/22

公开(公告)号：US3142041A

公开(公告)日：1964-07-21

申请号：US82279659

申请日：1959-06-25

Applicant: IBM

Inventor： MANCUSO JR PETER J

IPC: G06F9/22

CPC classification number: G06F9/22

公开(公告)号：US11726898B1

公开(公告)日：2023-08-15

申请号：US17731299

申请日：2022-04-28

Applicant: SPLUNK INC.

Inventor： Mayank Agarwal ,  Steven Karis ,  Justin Smith

IPC: G06F11/36 ,  G06F3/0482 ,  G06Q10/0639 ,  G06F9/22

CPC classification number: G06F11/3616 ,  G06F3/0482 ,  G06F11/3636 ,  G06F11/3664 ,  G06Q10/06395 ,  G06F9/22

Abstract: Monitoring and troubleshooting tools provide the capability to visualize different levels of a client's application that is deployed as a suite of independent but cooperating services (e.g., as microservices of a microservices-based architecture), collect values of monitored or tracked metrics at those different levels, and visualize values of the metrics at those levels. For example, metrics values can be generated for teams of the microservices.

公开(公告)号：US11726440B2

公开(公告)日：2023-08-15

申请号：US17352779

申请日：2021-06-21

Applicant: Honeywell International Inc.

Inventor： Paul Francis McLaughlin ,  Nagaraja Sundaresh ,  Joseph Pradeep Felix ,  Jethro Francis Steinman ,  Ram Mohan Anugu ,  Jason Thomas Urso ,  Joseph J Pane

IPC: G06F13/14 ,  G05B19/042 ,  G06F15/78 ,  G06F9/30 ,  G06F9/22 ,  G06F13/16

CPC classification number: G05B19/042 ,  G06F9/22 ,  G06F9/30 ,  G06F9/3012 ,  G06F13/14 ,  G06F13/161 ,  G06F15/7867 ,  G05B2219/21007

Abstract: A process control system includes a process controller level including at least one process controller, and an input/output (I/O) module level including at least one I/O module. The process controller level and the I/O module level are communicatively coupled. and each include control logic comprising control hardware or algorithm blocks. The control logic in the process controller level and the I/O module level are configured to execute and exchange data to perform process control for a process run by the process control system in a distributed fashion across the process controller level and the I/O module level.

公开(公告)号：US11675632B2

公开(公告)日：2023-06-13

申请号：US17133762

申请日：2020-12-24

Applicant: JPMorgan Chase Bank, N.A.

Inventor： Narayana Swamy Thota ,  Sumitra Nandan Mishra

IPC: G06F9/54 ,  G06F21/31 ,  G06F9/22 ,  G06F9/48 ,  H04B1/38

CPC classification number: G06F9/541 ,  G06F9/22 ,  G06F9/48 ,  G06F21/31 ,  H04B1/38

Abstract: Various methods, apparatuses/systems, and media for implementing a single window integrated platform are disclosed. A processor is operatively connected with one or more memories via a communication network. The processor receives a request from a user via a user computing device to develop a micro service; authenticates the user based on verifying login information of the user; receives information data related to the requested micro service; generates products application programming interface (API) to display selectable products based on the information data of the requested micro service. The processor also receives input on selected products; triggers a dynamic workflow based on the selected products; interacts with onboarding APIs to develop the micro service in response to the triggering of the dynamic workflow; and transmits a notification to the user computing device when an end state of the dynamic workflow is detected.