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公开(公告)号：US20180343244A1
公开(公告)日：2018-11-29
申请号：US16051794
申请日：2018-08-01
申请人： KARA PARTNERS LLC
发明人： Brian Penny , Desmond Penny
CPC分类号： H04L63/083 , G06F21/31 , H03M7/08 , H04L63/00 , H04L67/06
摘要： A system including: at least one processor; and at least one memory, having stored thereon computer program code that, when executed by the at least one processor, controls the at least one processor to: receive a first sequence of values; segment the first sequence of values into a first subsequence having a first length and a second subsequence having a second length; modify the first subsequence by inserting one or more values into the first subsequence to create a modified first subsequence of a third length; modify the second subsequence by one or more inserting values into the second subsequence to create a modified second subsequence of the third length; combine the modified first subsequence and the modified second subsequence to create a second sequence of values; and output the second sequence of values.
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公开(公告)号：US09797242B2
公开(公告)日：2017-10-24
申请号：US14280339
申请日：2014-05-16
发明人： Caimu Tang , Mark S. Beattie
摘要： A method for receiving an encoded integer includes acquiring a digitized waveform including a first plurality of pulses distributed among a second plurality of time slots, locating each of the pulses in the digitized waveform, computing a confidence value for each of the pulses, selecting a subset of the plurality of pulses, the subset including pulses having low confidence values computed, generating a set of unique waveforms corresponding to various combinations of the subset of pulses selected, computing a cross-correlation between each of the waveforms generated and the digitized waveform acquired, and selecting the waveform having the highest cross-correlation computed.
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公开(公告)号：US20100299378A1
公开(公告)日：2010-11-25
申请号：US12852036
申请日：2010-08-06
申请人： Klaus Kretzschmar , Nobuyoshi Mori
发明人： Klaus Kretzschmar , Nobuyoshi Mori
IPC分类号： G06F7/483
CPC分类号： G06F7/38 , G06F7/026 , G06F7/22 , G06F7/49 , G06F7/493 , G06F2207/4911 , H03M7/08 , H03M7/24
摘要： The invention comprises methods for manipulating floating point numbers on a microprocessor where the numbers are sortable. That is, the numbers obey lexicographical ordering. Hence, the numbers may be quickly compared using bit-wise comparison functions such as memcmp( ). Conversion may result in a sortable floating point number in the form of a sign, leading bits of the exponent, and sets of digit triples in the form of declets (sets of 10 bits). In a variable-length version, numbers may be compressed by storing the number of trailing zero declets in lieu of storing the zero declets themselves.
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公开(公告)号：US07797360B2
公开(公告)日：2010-09-14
申请号：US11400339
申请日：2006-04-06
申请人： Klaus Kretzschmar , Nobuyoshi Mori
发明人： Klaus Kretzschmar , Nobuyoshi Mori
IPC分类号： G06F7/00
CPC分类号： G06F7/38 , G06F7/026 , G06F7/22 , G06F7/49 , G06F7/493 , G06F2207/4911 , H03M7/08 , H03M7/24
摘要： The invention comprises methods for manipulating floating point numbers on a microprocessor where the numbers are sortable. That is, the numbers obey lexicographical ordering. Hence, the numbers may be quickly compared using bit-wise comparison functions such as memcmp( ). Conversion may result in a sortable floating point number in the form of a sign, leading bits of the exponent, and sets of digit triples in the form of declets (sets of 10 bits). In a variable-length version, numbers may be compressed by storing the number of trailing zero declets in lieu of storing the zero declets themselves.
摘要翻译： 本发明包括用于在微处理器上操作数字可排序的浮点数的方法。 也就是说，数字服从词典排序。 因此，可以使用诸如memcmp（）的比特比较功能快速比较数字。 转换可能导致一个可排序的浮点数，以符号的形式出现，引导位的指数，以及以十进位形式（10位的集合）形式的数字三元组。 在可变长度版本中，可以通过存储尾随的零个小区的数量代替存储零小区本身来压缩数字。
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公开(公告)号：US5892470A
公开(公告)日：1999-04-06
申请号：US780580
申请日：1997-01-08
申请人： Gregory P. Kusnick
发明人： Gregory P. Kusnick
CPC分类号： H03M7/08
摘要： A computer-based method and system for encoding a number as a sequence of words. The system has a table of words from which the words in the sequence are selected. Each word in the table has an index. To encode the number, the system first calculates an integer quotient of the number divided by a count of the words in the table and calculates a remainder of the number divided by the count of the words in the table. The system then repeats the following until the integer quotient is zero. The system selects the word in the table that is indexed by the remainder. The system then adds that word to the sequence. The system then calculates a new remainder of the integer quotient divided by the count of the words in the table and calculates a new integer quotient of the integer quotient divided by the count of the words in the table. The sequence of the words when complete represents the encoding of the number. The present invention also provides a computer-based method and system for decoding an encoding of a number to determine the number represented by the encoding. The system initializes the number to zero. The system then repeats the following for each word in the encoding. The system determines the index of the word in the table of words. The system multiplies the number by the count of words in the table. The system then adds the determined index to the number. When the process is complete, the number contains the value represented by the encoding.
摘要翻译： 一种基于计算机的方法和系统，用于将数字编码为字序列。 该系统具有从其中选择序列中的单词的单词表。 表中的每个字都有一个索引。 为了对该数进行编码，系统首先计算该数字的整数商除以该表中的单词的计数，并计算该数的余数除以该表中的单词的计数。 然后系统重复以下操作，直到整数商为零。 系统选择表中由剩余部分索引的单词。 然后系统将该字添加到序列中。 然后，系统计算整数商的新余数除以表中单词的计数，并计算整数商除以表中单词计数的新整数商。 完成时的单词序列表示数字的编码。 本发明还提供了一种基于计算机的方法和系统，用于解码数字的编码以确定由编码表示的数目。 系统将数字初始化为零。 然后，系统对编码中的每个单词重复以下。 系统确定单词表中单词的索引。 该系统将该数字乘以表中的单词计数。 然后系统将确定的索引添加到该号码。 当过程完成时，数字包含由编码表示的值。
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公开(公告)号：US4827261A
公开(公告)日：1989-05-02
申请号：US117213
申请日：1987-11-04
摘要： A clock-controlled pulse width modulator comprising an integrator for receiving a variable input voltage and producing an output having a triangular waveform, the integrator including a capacitor which is charged at a rate proportioal to the input voltage and discharged at a rate proportional to the difference between a reference voltage and the input voltage, the charging and discharging occurring during a time interval T.sub.o, a clock pulse source for generating a continuous series of clock pulses, a counter receiving the clock pulses and producing a binary control signal which changes state in response to the counting of a preselected number of clock pulses, the control signal having a period T.sub.o, and control means for terminating the charging of the capacitor and initiating the discharging of the capacitor in response to the first clock pulse following a selected transition in the control signal, and means for terminating the discharging of the capacitor and initiating the charging of the capacitor in response to the first clock pulse following the discharge of the capacitor to a preselected threshold level.
摘要翻译： 一种时钟控制脉冲宽度调制器，包括用于接收可变输入电压并产生具有三角波形的输出的积分器，该积分器包括以与输入电压成比例的比率充电并以与差值成比例的速率放电的电容器 在参考电压和输入电压之间，在时间间隔To期间发生的充电和放电，用于产生连续的一系列时钟脉冲的时钟脉冲源，接收时钟脉冲的计数器，并产生响应地改变状态的二进制控制信号 对预选数量的时钟脉冲进行计数，所述控制信号具有周期To，以及控制装置，用于终止电容器的充电，并且响应于控制中选择的转变后的第一时钟脉冲启动电容器的放电 信号和用于终止电容器放电并开始充电的装置 电容器响应于电容器放电到预选阈值水平之后的第一个时钟脉冲。
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公开(公告)号：US4295126A
公开(公告)日：1981-10-13
申请号：US193205
申请日：1980-10-02
CPC分类号： H03M7/08
摘要： A binary-to-decimal code converter consists of matrix-like arranged MOS transistors connected in series and parallel to each other in order to enable the optimum space arrangement on the chip.
摘要翻译： 二进制到十进制代码转换器由串联并联并联的矩阵状的MOS晶体管组成，以便能够在芯片上实现最佳的空间布置。
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公开(公告)号：US3862407A
公开(公告)日：1975-01-21
申请号：US10093370
申请日：1970-12-23
申请人： US NAVY
CPC分类号： H03M7/08
摘要： A decimal to binary converter which sequentially generates a train of pulses equal in number to each digit, of the decimal number to be converted, multiplied by its respective power of 10. These trains of pulses are then counted by a binary counter, the binary output of which is equivalent to the decimal input.
摘要翻译： 十进制到二进制转换器，其顺序地生成与要转换的十进制数的每个数字相等的脉冲序列，乘以其相应的功率10.这些脉冲序列然后由二进制计数器计数，二进制输出 其中相当于十进制输入。
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公开(公告)号：US3845290A
公开(公告)日：1974-10-29
申请号：US35287473
申请日：1973-04-20
申请人： PHILIPS CORP
发明人： REITSMA J
CPC分类号： H03M7/08
摘要： A digital decimal number is converted into a binary number by starting from the most signigicant digit, successively adding the coded digits to the part of the number which has been coded and which is multiplied by 10. The multiplication by 10 is effected as an addition of 8x and 2x the already coded part of the number, the multiplications by 8 and 2 being realized as shift operations over three bits and one bit, respectively. The addition of the newly added digit is effected by coding it in the bit locations which are vacated by the shift operations, any remaining bit being translated into an input carry.
摘要翻译： 通过从最重要的数字开始，将数字十进制数转换成二进制数，将编码的数字连续地添加到已被编码的数字的一部分并乘以10.乘以10作为加法 8x和2x已经编码的部分数字，8和2的乘法分别被实现为3位和1位的移位运算。 新添加的数字的添加通过在由移位操作腾空的位位置中进行编码来实现，任何剩余位被转换为输入进位。
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