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401.发明授权公开(公告)号：US11049561B2
公开(公告)日：2021-06-29
申请号：US16903264
申请日：2020-06-16
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Federico Goller , Cesare Torti , Marcella Carissimi , Emanuela Calvetti
Abstract: A method for programming a phase-change-memory device of a differential type comprises, in a first programming mode, supplying, during a first time interval, a same first programming current, of a type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said first programming current; and, in a second programming mode, supplying, during a second time interval, a same second programming current, of the other type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said second programming current, thus completing, in just two time steps, writing of a logic word in the memory device.
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402.发明申请公开(公告)号：US20210193220A1
公开(公告)日：2021-06-24
申请号：US17119979
申请日：2020-12-11
Applicant: STMicroelectronics S.r.l.
Abstract: In an embodiment, the column decoder of a PCM device is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.
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公开(公告)号：US20210188620A1
公开(公告)日：2021-06-24
申请号：US17126903
申请日：2020-12-18
Applicant: STMicroelectronics S.r.l.
Inventor： Luca SEGHIZZI , Nicolo' BONI , Laura OGGIONI , Roberto CARMINATI , Marta CARMINATI
Abstract: For manufacturing an optical microelectromechanical device, a first wafer of semiconductor material having a first surface and a second surface is machined to form a suspended mirror structure, a fixed structure surrounding the suspended mirror structure, elastic supporting elements which extend between the fixed structure and the suspended mirror structure, and an actuation structure coupled to the suspended mirror structure. A second wafer is machined separately to form a chamber delimited by a bottom wall having a through opening. The second wafer is bonded to the first surface of the first wafer in such a way that the chamber overlies the actuation structure and the through opening is aligned to the suspended mirror structure. Furthermore, a third wafer is bonded to the second surface of the first wafer to form a composite wafer device. The composite wafer device is then diced to form an optical microelectromechanical device.
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公开(公告)号：US20210187663A1
公开(公告)日：2021-06-24
申请号：US17121184
申请日：2020-12-14
Applicant: STMicroelectronics S.r.l.
Inventor： Antonio BELLIZZI , Michele DERAI
IPC: B23K26/38 , H01L21/304
Abstract: A semiconductor substrate such as a semiconductor wafer includes a cutting line having a length. The semiconductor substrate is cut along the line by first selectively applying laser beam ablation energy to the semiconductor substrate a certain locations along the cutting line and then blade sawing along cutting line. The semiconductor substrate thus includes one or more ablated regions as well as one or more unablated regions at the cutting line.
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公开(公告)号：US20210184576A1
公开(公告)日：2021-06-17
申请号：US17117847
申请日：2020-12-10
Applicant: STMicroelectronics S.r.l.
Inventor： Alberto CATTANI , Alessandro GASPARINI
Abstract: First and second n-channel FETs are connected in series between first and second terminals with an intermediate switching node. First and second driver circuits drive gates of the first and second n-channel FETs, respectively, in response to drive signals. The first driver circuit does not implement slew-rate control. A first resistor and capacitor are connected in series between the output of the first driver circuit and an intermediate node. A first electronic switch is connected between the intermediate node and the first terminal. A second electronic switch is connected between the intermediate node and the gate terminal of the first n-channel FET. A second resistor and a third electronic switch are connected in series between the gate terminal of the first n-channel FET and the switching node. A control circuit generates the drive signals and a first, second and third control signal for the first, second and third electronic switch.
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Patent Agency Ranking
公开(公告)号：US20210183849A1
公开(公告)日：2021-06-17
申请号：US17182773
申请日：2021-02-23
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Giuseppe PATTI
IPC: H01L27/02 , H01L29/10 , H01L29/78 , H01L29/417 , H01L29/66
Abstract: Power MOS device, in which a power MOS transistor has a drain terminal that is coupled to a power supply node, a gate terminal that is coupled to a drive node and a source terminal that is coupled to a load node. A detection MOS transistor has a drain terminal that is coupled to a detection node, a gate terminal that is coupled to the drive node and a source terminal that is coupled to the load node. A detection resistor has a first terminal coupled to the power supply node and a second terminal coupled to the detection node.
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407.发明授权公开(公告)号：US11038032B2
公开(公告)日：2021-06-15
申请号：US16990606
申请日：2020-08-11
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Vincenzo Enea
IPC: H01L29/417 , H01L29/10 , H01L29/78 , H01L29/66 , H01L21/3065 , H01L21/308 , H01L29/40 , H01L21/266 , H01L21/265
Abstract: A MOS transistor, in particular a vertical channel transistor, includes a semiconductor body housing a body region, a source region, a drain electrode and gate electrodes. The gate electrodes extend in corresponding recesses which are symmetrical with respect to an axis of symmetry of the semiconductor body. The transistor also has spacers which are also symmetrical with respect to the axis of symmetry. A source electrode extends in electrical contact with the source region at a surface portion of the semiconductor body surrounded by the spacers and is in particular adjacent to the spacers. During manufacture the spacers are used to form in an auto-aligning way the source electrode which is symmetrical with respect to the axis of symmetry and equidistant from the gate electrodes.
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公开(公告)号：US20210175753A1
公开(公告)日：2021-06-10
申请号：US17109345
申请日：2020-12-02
Applicant: STMicroelectronics S.r.l.
Inventor： Roberto LA ROSA , Alessandro FINOCCHIARO
Abstract: A first RF-to-DC circuit receives a radiofrequency signal and produces a first converted signal delivered to an energy storage circuit. A second RF-to-DC circuit, which is a down-scaled replica of the first RF-to-DC circuit, produces a second converted signal from the radiofrequency signal that is indicative of an open-circuit voltage of the first RF-to-DC circuit. The first RF-to-DC section includes N sub-stages, with a sub-set of sub-stages being selectively activatable. A window comparison of the second converted signal generates a first signal and a second signal indicative of whether the second converted signal is within a range of values proportional to a voltage reference signal. The sub-set of sub-stages is selectively deactivated, respectively activated, when the performed window comparison has a first result, respectively, a second result.
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公开(公告)号：US20210175350A1
公开(公告)日：2021-06-10
申请号：US17116465
申请日：2020-12-09
Applicant: STMicroelectronics S.r.l.
Inventor： Ferdinando IUCOLANO , Alessandro Chini
IPC: H01L29/778 , H01L29/40 , H01L29/205 , H01L29/20 , H01L29/66
Abstract: An HEMT transistor includes a semiconductor body having a semiconductive heterostructure. A gate region, of conductive material, is arranged above and in contact with the semiconductor body. A first insulating layer extends over the semiconductor body, laterally to the conductive gate region. A second insulating layer extends over the first insulating layer and the gate region. A first field plate region, of conductive material, extends between the first and the second insulating layers, laterally spaced from the conductive gate region along a first direction. A second field plate region, of conductive material, extends over the second insulating layer, and the second field plate region overlies and is vertically aligned with the first field plate region.
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410.发明授权公开(公告)号：US11032067B2
公开(公告)日：2021-06-08
申请号：US16022110
申请日：2018-06-28
Inventor： Roberto Colombo , Guido Marco Bertoni , William Orlando , Roberta Vittimani
Abstract: A hardware secure module includes a processing unit and a cryptographic coprocessor. The cryptographic coprocessor includes a key storage memory; a hardware key management circuit configured to store a first cryptographic key in the key storage memory; a first interface configured to receive source data to be processed; a second interface configured to receive the first cryptographic key from the processing unit for storing in the key storage memory; a hardware cryptographic engine configured to process the source data as a function of the first cryptographic key stored in the key storage memory; and a third interface configured to receive a second cryptographic key. The hardware secure module further includes a non-volatile memory configured to store the second cryptographic key; and a hardware configuration module configured to read the second cryptographic key from the non-volatile memory and send the second cryptographic key to the third interface.
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