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公开(公告)号：US20240363050A1
公开(公告)日：2024-10-31
申请号：US18029107
申请日：2022-06-29
IPC: G09G3/20 , G09G3/3233
CPC classification number: G09G3/2092 , G09G3/3233 , G09G2300/0842 , G09G2320/0257 , G09G2320/045
Abstract: Provided are a timing controller, sensing compensation method thereof, and display panel. The timing controller includes a sensing module (501), a built-in picture generation module (502), a multi-channel data selection module (503) and a processing output module (504). The sensing module is configured to sense whether a sensing compensation instruction is received, when received, notify built-in picture generation module and multi-channel data selection module; built-in picture generation module is configured to receive a notification and generate a first video signal; multi-channel data selection module is configured to receive a notification, switch from a display mode to a built-in picture mode, select first video signal as a video source, output first video signal to processing output module; processing output module is configured to process first video signal and output processed first video signal to the display panel so that the display panel performs sensing compensation based on the first video signal.
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公开(公告)号：US12118906B2
公开(公告)日：2024-10-15
申请号：US17764992
申请日：2021-05-28
Inventor： Xiaolong Wei , Fei Yang , Song Meng , Jingbo Xu , Jianbo Xian
IPC: G09G3/00 , G09G3/3233
CPC classification number: G09G3/006 , G09G3/3233 , G09G2300/0842
Abstract: A method for sensing a display panel includes: sensing an electrical characteristic parameter of a driving transistor of a pixel circuit of a sub-pixel in an X-th row in a blank stage between an N-th frame and an (N+1)-th frame, wherein X is a random number, and both N and X are positive integers.
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公开(公告)号：US20240321198A1
公开(公告)日：2024-09-26
申请号：US18034374
申请日：2022-06-29
Inventor： Min HE , Xiaolong WEI , Song MENG , Qiang FEI , Jingbo XU , Cheng XU , Miao LIU , Pengfei YIN
IPC: G09G3/3233 , G09G3/20
CPC classification number: G09G3/3233 , G09G3/2096 , G09G2300/0819 , G09G2300/0842 , G09G2320/103
Abstract: Disclosed are a display panel and a display method thereof, and a display apparatus. The display panel includes multiple pixel units, a pixel unit includes multiple sub-pixels, a sub-pixel includes a pixel drive circuit, a sense compensation circuit, and an element to be driven, and the display panel further includes a detection unit and a compensator; the pixel drive circuit is configured to drive the element to be driven in active time; the sense compensation circuit is configured to sense electrical characteristics of the element to be driven in blank time; the detection unit is configured to detect whether a currently displayed picture is a still picture, send a first notification to the compensator when the currently displayed picture is a still picture, and send a second notification to the compensator when the currently displayed picture is a non-still picture.
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公开(公告)号：US12100357B2
公开(公告)日：2024-09-24
申请号：US18466011
申请日：2023-09-13
Inventor： Xuehuan Feng , Yongqian Li
IPC: G09G3/3266 , G09G3/3225
CPC classification number: G09G3/3266 , G09G3/3225 , G09G2300/0426 , G09G2300/0842 , G09G2310/0286 , G09G2310/08 , G09G2320/0233 , G09G2320/0252 , G09G2320/0257 , G09G2320/029 , G09G2330/021
Abstract: A shift register, a gate drive circuit and a driving method therefor. The shift register includes a display pre-charge reset subcircuit, a sensing pre-charge reset subcircuit, a pull-down control subcircuit, an output subcircuit, a sensing cascade subcircuit and a black frame insertion cascade subcircuit. The display pre-charge reset subcircuit is configured to provide a signal of a first power supply end for a pull-up node under control of a first signal input end and provide a signal of a second power supply end to the pull-up node under control of a reset signal end; the sensing pre-charge reset subcircuit is configured to provide a signal of a first clock signal end to the pull-up node under control of the sensing cascade node and the first clock signal end, and provide a signal of the second power supply end to the pull-up node under control of a total reset end.
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公开(公告)号：US12062304B2
公开(公告)日：2024-08-13
申请号：US17262775
申请日：2020-06-02
Inventor： Zhidong Yuan , Yongqian Li , Can Yuan
CPC classification number: G09G3/006 , H01L27/0251 , H01L27/0292 , H01L27/124 , H01L27/1255 , G09G2300/0426 , G09G2310/0286
Abstract: An array substrate and a testing method thereof are provided. The array substrate includes a gate driving circuit, a plurality of clock signal lines and a plurality of testing terminals, wherein a number of the clock signal lines is greater than a number of the testing terminals; the plurality of clock signal lines are connected to the gate driving circuit and the plurality of testing terminals, and at least two clock signal lines are connected to a same testing terminal; and the plurality of testing terminals are configured to connect to a testing device.
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Patent Agency Ranking
公开(公告)号：US12057046B2
公开(公告)日：2024-08-06
申请号：US18313576
申请日：2023-05-08
Inventor： Xuehuan Feng , Yongqian Li
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes an input circuit, a first control circuit, a blanking control circuit, a first output circuit, and a second output circuit. The input circuit is configured to control a level of a first node; the first control circuit is configured to control a level of the second node; the blanking control circuit is configured to control the level of the first node and the level of the second node; the first output circuit is configured to output a first output signal at the first output terminal; and the second output circuit is configured to output a second output signal at the second output terminal under control of the level of the second node.
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437.发明授权公开(公告)号：US12040029B2
公开(公告)日：2024-07-16
申请号：US17776306
申请日：2021-05-26
Inventor： Can Yuan , Yongqian Li , Zhidong Yuan
IPC: G09G3/3225 , G11C19/28
CPC classification number: G11C19/28 , G09G3/3225 , G09G2300/0842 , G09G2310/0286 , G09G2310/08
Abstract: A shift register includes: an input circuit electrically connected to a first clock signal terminal, a first voltage signal terminal and a first node; a first output circuit electrically connected to the first node, a second clock signal terminal and a scanning signal terminal; a first control circuit electrically connected to a third clock signal terminal, a fourth clock signal terminal, a fifth clock signal terminal and the first node; a second control circuit electrically connected to a sixth clock signal terminal, a second voltage signal terminal, the first node, the first voltage signal terminal and a second node; a third control circuit electrically connected to the first node, the second voltage signal terminal, the third clock signal terminal and the second node; and a second output circuit electrically connected to the second node, the second voltage signal terminal and the scanning signal terminal.
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公开(公告)号：US20240237484A1
公开(公告)日：2024-07-11
申请号：US17997027
申请日：2021-10-29
Inventor： Xinwei Gao , Peng Li , Shuai Zhang
IPC: H10K59/80 , H10K59/122
CPC classification number: H10K59/873 , H10K59/122
Abstract: A mother board for a display panel, having a bonding region and a first panel region including a retaining region and a peripheral region, in which: a first light-emitting functional layer is located in the first panel region; a first adhesive layer surrounding the first panel region is adhered to a cover plate and a base substrate, and an orthographic projection of an edge of the first adhesive layer close to the bonding region on the base substrate defines a first pattern; the first light-emitting functional layer in the retaining region and the peripheral region are spaced by a first spacing layer, an orthographic projection of which on the base substrate partially overlaps with the first pattern and form a closed second pattern therewith. The orthographic projection of the first spacing layer on the base substrate is located within that of the first adhesive layer on the base substrate.
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公开(公告)号：US20240215422A1
公开(公告)日：2024-06-27
申请号：US17791262
申请日：2021-09-28
Inventor： Zhidong YUAN , Pan XU , Yongqian LI , Can YUAN
IPC: H10K59/88 , G01R31/28 , G09G3/3233 , G09G3/3266 , H10K71/70
CPC classification number: H10K59/88 , G01R31/2884 , G09G3/3233 , G09G3/3266 , H10K71/70 , G09G2300/0408 , G09G2300/0842 , G09G2310/0286 , G09G2310/08 , G09G2330/12
Abstract: A display panel, and a test method thereof, a display apparatus, each subpixel of the pixel array of the display panel includes a pixel circuit, a first signal line configured to provide a scanning signal to the pixel circuit, a scan driver circuit configured to provide the scanning signal to the pixel circuit and includes a shift register and a clock signal line in the display area; a test circuit board in the non-display area and including a test pad; and a test lead in the non-display area and electrically connected with the test pad. The first signal line includes a first part in the display area and a second part in the non-display area, the first part extends substantially along the first direction.
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公开(公告)号：US20240177663A1
公开(公告)日：2024-05-30
申请号：US17789938
申请日：2021-07-09
Inventor： Yongqian LI , Can YUAN , Zhongyuan WU
IPC: G09G3/3233 , H10K59/131
CPC classification number: G09G3/3233 , H10K59/131 , G09G2300/0408 , G09G2300/0452 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/08
Abstract: A display substrate and a display panel are provided. The display substrate includes: a base substrate; and a plurality of sub-pixels. Each sub-pixel includes a light-emitting element and a pixel circuit; the pixel circuit includes a driving circuit, a data writing circuit, a first control circuit, a second control circuit, and a light-emitting control circuit; the driving circuit is configured to control the driving current flowing through the light-emitting element; the light-emitting control circuit is configured to apply the driving current to the light-emitting element; the first control circuit is configured to write a reference voltage into the driving circuit; the second control circuit is configured to write an initial voltage into the first electrode of the light-emitting element; and orthographic projections of at least part of pixel circuits of every two adjacent sub-pixels in a same row of sub-pixels on the base substrate are mirror-symmetrical.
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