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431.发明授权公开(公告)号：US11049419B2
公开(公告)日：2021-06-29
申请号：US16186820
申请日：2018-11-12
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Alexandre Sarafianos , Thomas Ordas , Yanis Linge
IPC: G09C1/00 , H03K19/003 , H04L9/00 , G06F21/75
Abstract: In an embodiment, a circuit includes a supply terminal, a reference terminal, a logic circuit coupled between the supply terminal and the reference terminal, and an auxiliary circuit coupled to the logic circuit. The auxiliary circuit includes a plurality of switches configured to be controlled to produce random criterions. Each random criterion causes, on each transition of an output signal of the logic, an attenuation of a current flowing between a supply terminal of the circuit and a reference terminal of the circuit; or an increase of the current flowing between the supply terminal of the circuit and the reference terminal of the circuit; or an additional current flowing through the logic circuit on a current path not passing through the supply terminal; or no change in the current flowing between the supply terminal of the circuit and the reference terminal of the circuit.
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公开(公告)号：US20210192492A1
公开(公告)日：2021-06-24
申请号：US17127269
申请日：2020-12-18
Inventor： Olivier VAN NIEUWENHUYZE , Jean-Marc GRIMAUD
Abstract: A method of configuring a contactless communication device is provided. The contactless communication device includes integrated circuits hosting at least two applications compatible with the same communication protocols or compatible with the same communication protocol and using different communication parameters and a contactless communication circuit. The method includes detecting, by the contactless communication circuit, an interruption of a transaction initiated by a proximity coupling reader.
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公开(公告)号：US20210192304A1
公开(公告)日：2021-06-24
申请号：US17126830
申请日：2020-12-18
Inventor： Julien MERCIER , Pascal NONIER
IPC: G06K19/07
Abstract: A method of managing the power supply of one or more first elements by a second element of a same first device, includes the steps of: sending, to a second device, a time extension request; evaluating during the time extension a power available from an electromagnetic field radiated by the second device; and adjusting the power supply of the second element and of the first element(s) according to the available power.
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434.发明申请公开(公告)号：US20210181778A1
公开(公告)日：2021-06-17
申请号：US17119788
申请日：2020-12-11
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jimmy Fort , Nicolas Demange
Abstract: An embodiment method for smoothing consumed current is based on a current copying suite and on a current source supplying a reference current, the currents being transformed into a reference voltage for the regulation of a voltage regulator such that the consumed current viewed by the power supply only depends on the reference current.
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公开(公告)号：US20210159308A1
公开(公告)日：2021-05-27
申请号：US17165013
申请日：2021-02-02
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Abderrezak MARZAKI
IPC: H01L49/02 , H01L27/11517 , H01L29/06
Abstract: A capacitive element of an integrated circuit includes first and second electrodes. The first electrode is formed by a first electrically conductive layer located above a semiconductor well doped with a first conductivity type. The second electrode is formed by a second electrically conductive layer located above the first electrically conductive layer of the semiconductor well. The second electrode is further formed by a doped surface region within the semiconductor well that is heavily doped with a second conductivity type opposite the first conductivity type, wherein the doped surface region is located under the first electrically conductive layer. An inter-electrode dielectric area electrically separates the first electrode and the second electrode.
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Patent Agency Ranking
公开(公告)号：US20210158887A1
公开(公告)日：2021-05-27
申请号：US17096090
申请日：2020-11-12
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Christophe Eva , Jean-Michel Gril-Maffre
Abstract: An embodiment method for writing to a volatile memory comprises at least receiving a request to write to the memory, and, in response to each request to write to the memory: preparation of data to be written to the memory, this comprising computing an error correction code; storing in a buffer register the data to be written to the memory; and, if no new request to write to or to read from the memory is received after the storage, writing to the memory of the data to be written stored in the buffer register.
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公开(公告)号：US11005514B2
公开(公告)日：2021-05-11
申请号：US16844246
申请日：2020-04-09
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Nicolas Cordier
Abstract: An amplification circuit includes a first group of amplifiers including N first amplifiers, a second group of amplifiers including K second amplifiers, a first terminal, a second terminal, and a third terminal. Each of the N first amplifiers and each of the K second amplifiers includes an output. The second group of amplifiers is divided into a first subassembly of amplifiers and a second subassembly of amplifiers. The first subassembly includes M second amplifiers of the second group. The second subassembly includes K-M remaining second amplifiers of the second group. The first terminal is coupled to each output of the N first amplifiers and to a first radio frequency output terminal. The second terminal is coupled to each output of the M second amplifiers. The third terminal is coupled to each output of the K-M second remaining amplifiers and to a second radio frequency output terminal.
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公开(公告)号：US11003595B2
公开(公告)日：2021-05-11
申请号：US16841403
申请日：2020-04-06
Inventor： Michael Peeters , Fabrice Marinet , Jean-Louis Modave
Abstract: A non-volatile memory is organized in pages and has a word writing granularity of one or more bytes and a block erasing granularity of one or more pages. Logical addresses are scrambling into physical addresses used to perform operations in the non-volatile memory. The scrambling includes scrambling logical data addresses based on a page structure of the non-volatile memory and scrambling logical code addresses based on a word structure of the non-volatile memory.
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公开(公告)号：US10998378B2
公开(公告)日：2021-05-04
申请号：US16543124
申请日：2019-08-16
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Philippe Boivin , Jean-Jacques Fagot
IPC: H01L29/423 , H01L27/24 , H01L21/28 , H01L29/66 , H01L21/762 , H01L29/78 , H01L45/00
Abstract: A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.
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公开(公告)号：US10998306B2
公开(公告)日：2021-05-04
申请号：US16100796
申请日：2018-08-10
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Daniele Fronte , Pierre-Yvan Liardet , Alexandre Sarafianos
Abstract: A circuit for protecting an integrated circuit against fault injection attacks includes an element including a dielectric which is destroyed, resulting in the occurrence of a short-circuit. The element is connected between two terminals that receive a power supply voltage of the integrated circuit.
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