公开(公告)号：US20220385590A1

公开(公告)日：2022-12-01

申请号：US17336080

申请日：2021-06-01

Applicant: Mellanox Technologies, Ltd.

Inventor： Zachy Haramaty ,  Liron Mula ,  Alon Singer ,  Eduard Kvetny ,  Aviv Kfir

IPC: H04L12/801 ,  H04L12/861 ,  H04L12/707 ,  H04L29/06

Abstract: An apparatus includes an input interface to receive incoming packets from a first network device and an output interface to send outgoing packets to a second network device. Media access control security (MACsec) circuitry is coupled between the input interface and the output interface. Bypass flow-control (FC) circuitry is coupled between the input interface and the MACsec circuitry. The bypass FC circuitry is to detect an FC packet in the incoming packets and pass the FC packet passively to the output interface to enable end-to-end flow control directly between the first network device and the second network device.

公开(公告)号：US20220377014A1

公开(公告)日：2022-11-24

申请号：US17874352

申请日：2022-07-27

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Avi Urman ,  Lior Narkis ,  Noam Bloch

IPC: H04L45/745 ,  H04L69/22 ,  G06F13/42

Abstract: A communication apparatus includes a host interface, connected to a peripheral component bus so as to communicate with a CPU and a memory of a host computer. A network interface is connected to a network. Packet processing circuitry is configured to receive from a first interface a data packet including a set of one or more headers that include header fields having respective values, to identify, responsively to at least one of the header fields, a corresponding entry in a header modification table that specifies a header modification operation, to modify the set of headers in accordance with the header modification operation, to check whether the entry specifies an additional header modification operation, to output the modified set of headers if the entry does not specify an additional header modification operation, and, if the entry specifies an additional header modification operation, to feed-back the modified set of headers.

公开(公告)号：US11497136B2

公开(公告)日：2022-11-08

申请号：US16502686

申请日：2019-07-03

Applicant: Mellanox Technologies, Ltd.

Inventor： Avner Badihi ,  Eyal Babish

IPC: H05K7/20 ,  H05K7/10

Abstract: A universal replaceable fan unit and method of reversing an airflow direction of a universal replaceable fan unit is provided. The universal replaceable fan unit includes a fan assembly designed to create an airflow from an intake end to an output end. The universal replaceable fan unit also includes a fan mounting that receives and secures the fan assembly in an operable position. The fan mounting includes a frame member and a securing member. The fan mounting is designed to allow the fan assembly to be moved between a first position defining a first airflow direction and a second position defining a second airflow direction. The first airflow direction is opposite the second airflow direction. The universal replaceable fan unit further includes an electrical connector removably attached to the fan assembly. The electrical connector allows electricity to be provided to the fan assembly for operation.

公开(公告)号：US20220350506A1

公开(公告)日：2022-11-03

申请号：US17244579

申请日：2021-04-29

Applicant: Mellanox Technologies LTD.

Inventor： Barak Gafni ,  Aviv Kfir

IPC: G06F3/06

Abstract: Devices, methods, and systems are provided. In one example, a device is described to include a bandwidth-constrained resource and a controller that dynamically allocates a proportional consumption of storage to the bandwidth-constrained resource thereby enabling the bandwidth-constrained resource to provide bandwidth to a consuming entity. The controller may allocate the proportional consumption of the storage to the bandwidth-constrained resource based on a current state of the bandwidth-constrained resource.

公开(公告)号：US11487066B2

公开(公告)日：2022-11-01

申请号：US17117867

申请日：2020-12-10

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Elad Mentovich ,  Yaakov Gridish ,  Anna Sandomirsky ,  Alon Rubinstein ,  Nimrod Rockman ,  Dimitrios Kalavrouziotis

IPC: G02B6/42 ,  H04B10/25 ,  H04B10/40

Abstract: A package includes a light emitting portion configured to emit light, a lens including a first lens surface and a second lens surface, a protective layer between the light emitting portion and the first lens surface and that shields the first lens surface from a surrounding environment, and an optical component that redirects light output from the second lens surface. The first lens surface is configured to receive the emitted light from the light emitting portion, the second lens surface is configured output light that has passed through the first lens surface, and the protective layer has a refractive index greater than 1.5.

公开(公告)号：US11476928B2

公开(公告)日：2022-10-18

申请号：US16921993

申请日：2020-07-07

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan David Levi ,  Avi Urman ,  Lior Narkis ,  Liron Mula ,  Paraskevas Bakopoulos ,  Ariel Almog ,  Roee Moyal ,  Gal Yefet

IPC: H04B7/26 ,  H04L49/351 ,  H04L49/90 ,  H04W72/04 ,  H04W74/08

Abstract: A network element one or more network ports, network time circuitry and packet processing circuitry. The network ports are configured to communicate with a communication network. The network time circuitry is configured to track a network time defined in the communication network. In some embodiments the packet processing circuitry is configured to receive a definition of one or more timeslots that are synchronized to the network time, and to send outbound packets to the communication network depending on the timeslots. In some embodiments the packet processing circuitry is configured to process inbound packets, which are received from the communication network, depending on the timeslots.

公开(公告)号：US11469768B2

公开(公告)日：2022-10-11

申请号：US17188696

申请日：2021-03-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Igal Kushnir ,  Eshel Gordon ,  Roi Levi

IPC: H03M1/66 ,  H04B1/04

Abstract: A digital to analog converter (DAC) includes a first amplifier configured to receive a first bit of a data block as an input and output a first signal based on a value of the first bit of the data block, a first filter circuit configured to filter the first signal, an output configured to output an analog signal based on a combination of the filtered first signal and a second signal that represents a value of a second bit of the data block.

公开(公告)号：US11456805B2

公开(公告)日：2022-09-27

申请号：US17438143

申请日：2019-05-08

Applicant: Mellanox Technologies, Ltd.

Inventor： Don Becker ,  Dmitrios Kalavrouziotis ,  Paraskevas Bakopoulos ,  Vladimr Iakolev ,  Elad Mentovich

IPC: H04B10/61 ,  H04B10/67 ,  H04B10/2569 ,  H04B10/60 ,  H04B10/43 ,  H04B10/50 ,  H04B10/40

Abstract: A passive dual polarization unit and coherent transceiver and/or receiver including one or more passive dual polarization units are provided. An example passive dual polarization unit includes a polarization splitter configured to split an input signal into a TE mode and TM mode signals; TE/TM splitters each designed to split the TE/TM mode signals into first TE/TM signals and second TE/TM signals; a first TE signal polarization rotation component for receiving the first TE signal and providing a third TM signal having the same magnitude and time dependence as the first TE signal; a first TM signal polarization rotation component for receiving the first TM signal and providing a third TE signal having the same magnitude and time dependence as the first TM signal; and TE/TM couplers that couple the second TE/TM signals and the third TE/TM signals to generate output TE/TM signals.

公开(公告)号：US20220293500A1

公开(公告)日：2022-09-15

申请号：US17199025

申请日：2021-03-11

Applicant: Mellanox Technologies, Ltd.

Inventor： Pavel Vilner ,  Dmitry Fliter ,  Jacov Brener

IPC: H01L23/498 ,  H01L23/31 ,  H05K3/34

Abstract: Embodiments are disclosed for providing a ball grid array pattern for an integrated circuit. An example integrated circuit apparatus includes an integrated circuit and a ball grid array. The integrated circuit includes at least a package substrate and a silicon chip. The ball grid array is disposed on the package substrate of the integrated circuit. The ball grid array includes a first set of solder balls that is configured to provide electrical connections for communication channels and a second set of the solder balls associated with an electrical ground. The first set of solder balls includes a first subset of solder balls configured in a first orientation and a second subset of solder balls configured in a second orientation. Furthermore, at least one solder ball from the second set of the solder balls is disposed between the first subset of solder balls and the second subset of solder balls.

公开(公告)号：US20220283973A1

公开(公告)日：2022-09-08

申请号：US17636484

申请日：2019-08-21

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan LEVI ,  Elad MENTOVICH ,  Ran RAVID ,  Roee SHAPIRO ,  Avraham GANOR ,  Paraskevas BAKOPOULOS ,  Dimitrios KALAVROUZIOTIS

IPC: G06F13/40 ,  G06F13/42

Abstract: Apparatuses, systems, and associated methods of manufacturing are described that provide a dynamic data interconnect and networking cable configuration. The dynamic data interconnect includes a substrate, transmitters supported on the substrate configured to generate signals, and receivers supported on the substrate configured to receive signals. The dynamic data interconnect further includes a number of connection pads that receive data cables attached thereto and a number of transmission lanes that operably couple the transmitters and receivers to the connection pads. The dynamic data interconnect further includes transmission circuitry in communication with each of the transmitters and receivers such that, in an operational configuration, the transmission circuitry determines a transmission state of the dynamic data interconnect and selectively disables operation of at least a portion of the transmitters or at least a portion of the receivers.