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    Analysis of events in an integrated circuit using cause tree and buffer
    1.
    发明授权
    Analysis of events in an integrated circuit using cause tree and buffer 有权

    公开(公告)号：US11966310B1

    公开(公告)日：2024-04-23

    申请号：US17981508

    申请日：2022-11-07

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Alon Singer ,  Ziv Battat ,  Liron Mula

    IPC: G06F11/00 ,  G06F11/07 ,  G06F11/30 ,  G06F11/34

    CPC classification number: G06F11/3037 ,  G06F11/079 ,  G06F11/3075 ,  G06F11/3409

    Abstract: An Integrated Circuit (IC) includes one or more functional hardware circuits, one or more processor cores, a cause-tree circuit, a memory buffer, and an analysis circuit. The processor cores are to handle events occurring in the functional hardware circuits. The cause-tree circuit includes leaf nodes, middle nodes and a root node. The leaf nodes are to collect the events from the one or more functional hardware circuits. The middle nodes are to coalesce the collected events and to deliver the events to the root node. The memory buffer is to buffer a plurality of the events delivered to the root node, so as to trigger the processor cores to handle the buffered events. The buffer analysis circuit is to analyze a performance of the cause-tree circuit based on the events buffered in the memory buffer.

    Out-Of-Order Input / Output Write
    3.
    发明公开
    Out-Of-Order Input / Output Write 审中-公开

    公开(公告)号：US20230376314A1

    公开(公告)日：2023-11-23

    申请号：US17748066

    申请日：2022-05-19

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Alon Singer ,  Zachy Haramaty

    IPC: G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3836 ,  G06F9/30145 ,  G06F9/30101 ,  G06F9/30189

    Abstract: A System-On-Chip (SoC) includes a set of registers, a processor, and Out-Of-Order Write (OOOW) circuitry. The processor is to execute instructions including write instructions. After issuing a first write instruction to any of the registers in the set, the processor is to await an acknowledgement for the first write instruction before issuing a second write instruction to any of the registers in the set. The OOOW circuitry is to identify the write instructions issued by the processor to the registers in the set, to perform the identified write instructions in the registers irrespective of acknowledgements from the registers, and to send to the processor imitated acknowledgements for the identified write instructions.

    Integrated-Circuit Memory Dump using Hardware Security Mechanism
    5.
    发明申请
    Integrated-Circuit Memory Dump using Hardware Security Mechanism 有权

    公开(公告)号：US20240370592A1

    公开(公告)日：2024-11-07

    申请号：US18309839

    申请日：2023-05-01

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Alon Singer ,  Zachy Haramaty

    IPC: G06F21/78 ,  G06F21/60

    Abstract: A device includes multiple registers, multiple hardware-implemented Privilege Level Indicators (PLIs), and one or more circuits. The registers are to store respective values. The PLIs are to specify privilege levels for accessing the respective registers. The one or more circuits are to perform a secure memory dump operation including (i) checking the PLIs of one or more of the registers and (ii) outputting the values of the registers that are permitted for outputting according to the respective PLIs.

    Processor with Split Read
    6.
    发明申请
    Processor with Split Read 有权

    公开(公告)号：US20230004392A1

    公开(公告)日：2023-01-05

    申请号：US17367367

    申请日：2021-07-04

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Zachy Haramaty ,  Yaniv Strassberg ,  Itsik Levi ,  Alon Singer

    IPC: G06F9/30 ,  G06F12/02

    Abstract: An apparatus includes a processor and split-read control circuitry (SRCC). The processor is to issue a set of one or more split-read requests for loading one or more data values to one or more respective local registers of the processor. The SRCC is to receive the set of one or more split-read requests, to read the one or more data values on behalf of the processor, and to write the data values into the one or more respective local registers. The processor and the SRCC are to coordinate a status of the split-read requests via a split-read-status indication.

    Analysis of Events in an Integrated Circuit Using Cause Tree and Buffer
    7.
    发明公开
    Analysis of Events in an Integrated Circuit Using Cause Tree and Buffer 审中-公开

    公开(公告)号：US20240152438A1

    公开(公告)日：2024-05-09

    申请号：US17981508

    申请日：2022-11-07

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Alon Singer ,  Ziv Battat ,  Liron Mula

    IPC: G06F11/30 ,  G06F11/07 ,  G06F11/34

    CPC classification number: G06F11/3037 ,  G06F11/079 ,  G06F11/3075 ,  G06F11/3409

    Abstract: An Integrated Circuit (IC) includes one or more functional hardware circuits, one or more processor cores, a cause-tree circuit, a memory buffer, and an analysis circuit. The processor cores are to handle events occurring in the functional hardware circuits. The cause-tree circuit includes leaf nodes, middle nodes and a root node. The leaf nodes are to collect the events from the one or more functional hardware circuits. The middle nodes are to coalesce the collected events and to deliver the events to the root node. The memory buffer is to buffer a plurality of the events delivered to the root node, so as to trigger the processor cores to handle the buffered events. The buffer analysis circuit is to analyze a performance of the cause-tree circuit based on the events buffered in the memory buffer.

    Out-of-order input / output write
    8.
    发明授权
    Out-of-order input / output write 有权

    公开(公告)号：US11847461B2

    公开(公告)日：2023-12-19

    申请号：US17748066

    申请日：2022-05-19

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Alon Singer ,  Zachy Haramaty

    IPC: G06F9/38 ,  G06F9/30 ,  G06F13/16

    CPC classification number: G06F9/3836 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/30189 ,  G06F13/16

    Abstract: A System-On-Chip (SoC) includes a set of registers, a processor, and Out-Of-Order Write (OOOW) circuitry. The processor is to execute instructions including write instructions. After issuing a first write instruction to any of the registers in the set, the processor is to await an acknowledgement for the first write instruction before issuing a second write instruction to any of the registers in the set. The OOOW circuitry is to identify the write instructions issued by the processor to the registers in the set, to perform the identified write instructions in the registers irrespective of acknowledgements from the registers, and to send to the processor imitated acknowledgements for the identified write instructions.

    Processor with split read
    9.
    发明授权
    Processor with split read 有权

    公开(公告)号：US11734005B2

    公开(公告)日：2023-08-22

    申请号：US17367367

    申请日：2021-07-04

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Zachy Haramaty ,  Yaniv Strassberg ,  Itsik Levi ,  Alon Singer

    IPC: G06F9/30 ,  G06F12/02

    CPC classification number: G06F9/30101 ,  G06F12/023 ,  G06F2212/251

    Abstract: An apparatus includes a processor and split-read control circuitry (SRCC). The processor is to issue a set of one or more split-read requests for loading one or more data values to one or more respective local registers of the processor. The SRCC is to receive the set of one or more split-read requests, to read the one or more data values on behalf of the processor, and to write the data values into the one or more respective local registers. The processor and the SRCC are to coordinate a status of the split-read requests via a split-read-status indication.

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