公开(公告)号：US20060251250A1

公开(公告)日：2006-11-09

申请号：US11381474

申请日：2006-05-03

Applicant: Davide Ruggiero ,  Danilo Mascolo ,  Immacolata Pedaci ,  Paolo Amato

Inventor： Davide Ruggiero ,  Danilo Mascolo ,  Immacolata Pedaci ,  Paolo Amato

IPC: H04L9/00

CPC classification number: H04L9/001 ,  H04L9/0662 ,  H04L2209/12

Abstract: A method for generating a succession of pseudo-random numbers includes choosing at least one chaotic map, and choosing a seed for the chaotic map and a number of iterations for the chaotic map. The succession of pseudo-random numbers are generated by executing iteratively generating a pseudo-random number as a function of a final state reached by the chaotic map iterated for the current number of iterations starting from the current seed, and generating a new seed for the chaotic map or a new number of iterations as a function of the final state.

Abstract translation: 一种用于产生连续的伪随机数的方法包括选择至少一个混沌映射，以及为混沌映射选择种子和混沌映射的迭代次数。 伪随机数的连续性是通过执行迭代地产生伪随机数作为由当前种子开始的当前迭代次数迭代的混沌映射所达到的最终状态的函数而产生的，并且为 混沌映射或新数量的迭代作为最终状态的函数。

公开(公告)号：US20060232337A1

公开(公告)日：2006-10-19

申请号：US11388249

申请日：2006-03-23

Applicant: Carlo Caminada ,  Ernesto Lasalandra

Inventor： Carlo Caminada ,  Ernesto Lasalandra

IPC: H03F3/45

CPC classification number: H03F3/45659

Abstract: A fully differential amplifier device includes a first input and a second input, a first output and a second output, and a differential input stage, provided with a first input transistor and a second input transistor. The first input and the first output and the second input and the second output are directly connected selectively in a first operating configuration and disconnected in a second operating configuration. The amplifier device further includes a current-generator circuit connected so as to supply respective first currents to the first and second outputs irrespective of a state of conduction of the first and second input transistors.

Abstract translation: 全差分放大器装置包括第一输入和第二输入，第一输出和第二输出以及具有第一输入晶体管和第二输入晶体管的差分输入级。 第一输入和第一输出以及第二输入和第二输出被选择性地直接连接在第一操作配置中并在第二操作配置中断开。 放大器装置还包括电流发生器电路，其连接以便将第一电流提供给第一和第二输出，而与第一和第二输入晶体管的导通状态无关。

公开(公告)号：US20060230821A1

公开(公告)日：2006-10-19

申请号：US11367806

申请日：2006-03-03

Applicant: Ferdinando Taglialatela-Scafati ,  Nicola Cesario ,  Giovanni Di Lorenzo

Inventor： Ferdinando Taglialatela-Scafati ,  Nicola Cesario ,  Giovanni Di Lorenzo

IPC: G01L3/26

CPC classification number: G01M15/11

Abstract: A method of diagnosing misfire or partial combustion conditions in an internal combustion engine without using a phonic wheel discriminates the combustion conditions with soft-computing techniques directly exploiting a combustion pressure signal generated by a common pressure sensor installed in the cylinder. There exists an exploitably close correlation between the instantaneous values of the internal cylinder pressure and the occurrence of misfire or partial combustion conditions, and thus the cylinder pressure signal may be reliably used for diagnosing misfires or partial combustions in functioning conditions of the engine.

Abstract translation: 在不使用声轮的情况下诊断内燃机中的失火或部分燃烧条件的方法通过直接利用安装在气缸中的公共压力传感器产生的燃烧压力信号的软计算技术来识别燃烧条​​件。 在内部汽缸压力的瞬时值与失火或部分燃烧条件的发生之间存在着可靠的紧密的相关性，因此，气缸压力信号可以可靠地用于诊断发动机的运转状态下的失火或部分燃烧。

公开(公告)号：US20060227610A1

公开(公告)日：2006-10-12

申请号：US11279384

申请日：2006-04-11

Applicant: Luigi Pascucci ,  Paolo Rolandi

Inventor： Luigi Pascucci ,  Paolo Rolandi

IPC: G11C16/04

CPC classification number: G11C16/08 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  Y10T29/49002

Abstract: A non-volatile memory electronic device is integrated on a semiconductor and is of the Flash EEPROM type with an architecture of the NAND type including at least one memory matrix divided into sectors being singularly erasable and organized in rows or word lines and columns or bit lines of memory cells. Advantageously, the matrix may include logic sectors wherein pairs of rows or word lines are electrically short-circuited and refer to a single biasing terminal, source terminals of the associated cells of each pair of rows associated with a same source select line referring to a corresponding biasing terminal, and at least one pair of independent drain select lines, each of the rows and of the lines being provided with metallization shunts to by-pass groups of bit lines and/or to speed up the propagation times of the biasing in the corresponding logic sector.

Abstract translation: 非易失性存储器电子器件集成在半导体上，并且是具有NAND型结构的闪存EEPROM类型，包括被划分成扇区的至少一个存储器矩阵，其被单独地擦除并且被组织成行或字线和列或位线 的记忆细胞。 有利地，矩阵可以包括其中行或字线对被电短路并且指代单个偏置端子的逻辑扇区，每对行的相关联的单元的源极端子与相应的源选择线相关联，其指向相应的 偏置端子以及至少一对独立的漏极选择线，行和行中的每一行被设置有金属化分流器以逐行排列组和/或加速相应的偏置的传播时间 逻辑部门。

公开(公告)号：US20060213267A1

公开(公告)日：2006-09-28

申请号：US11291080

申请日：2005-11-30

Applicant: Michele Tronconi ,  Enrico Chiesa ,  Fabio Pasolini

Inventor： Michele Tronconi ,  Enrico Chiesa ,  Fabio Pasolini

IPC: G01P1/00 ,  G01P15/00

CPC classification number: G11B19/04 ,  G01P15/0891 ,  G01P15/18

Abstract: In a displacement detection device, an acceleration sensor generates at least a first acceleration signal relating to an axis of detection, and a displacement detection circuit is connected to the acceleration sensor has a comparator stage for comparing the acceleration signal with a programmable acceleration threshold and generates a displacement-detection signal. A high-pass filter is arranged between the acceleration sensor and the comparator stage so as to reduce a DC component of the acceleration signal. The cut-off frequency of the high-pass filter is modified according to the type of displacements that are to be detected.

Abstract translation: 在位移检测装置中，加速度传感器至少产生与检测轴相关的第一加速度信号，并且与加速度传感器连接的位移检测电路具有比较器级，用于将加速度信号与可编程加速度阈值进行比较，并产生 位移检测信号。 在加速度传感器和比较器级之间布置有高通滤波器，以减小加速度信号的直流分量。 高通滤波器的截止频率根据要检测的位移类型进行修改。

公开(公告)号：US20060181355A1

公开(公告)日：2006-08-17

申请号：US11058439

申请日：2005-02-14

Applicant: Tino Copani ,  Santo Smerzi ,  Giovanni Girlando ,  Giuseppe Palmisano

Inventor： Tino Copani ,  Santo Smerzi ,  Giovanni Girlando ,  Giuseppe Palmisano

IPC: H03J7/02

CPC classification number: H03B5/1231 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1296

Abstract: A silicon bipolar VCO implementing a double-coupled transformer is disclosed. The VCO circuit, which is suitable in the field of integrated RF circuits, has been integrated into a universal LNB having a down-converter block and PLL merged into a single die and implemented in silicon bipolar technology. The integrated transformer is formed by three turns of stacked metal layers, where the topmost metal layer is employed for the resonator inductance. The VCO is missing conventional biasing resistors and decoupling capacitors, thus improving phase noise and tuning range performance.

Abstract translation: 公开了实现双耦合变压器的硅双极型VCO。 适用于集成RF电路领域的VCO电路已经被集成到具有下变频器模块和PLL的通用LNB中，该LNB被并入单个芯片并且以硅双极技术实现。 集成式变压器由三层堆叠的金属层形成，其中最顶层的金属层用于谐振器电感。 VCO缺少传统的偏置电阻和去耦电容，从而改善了相位噪声和调谐范围的性能。

公开(公告)号：US20060176203A1

公开(公告)日：2006-08-10

申请号：US11352104

申请日：2006-02-10

Applicant: Antonio Grosso ,  Cristiano Meroni ,  Edoardo Botti

Inventor： Antonio Grosso ,  Cristiano Meroni ,  Edoardo Botti

IPC: H03M1/66

CPC classification number: H03M1/70

Abstract: A digital-to-analog converter (DAC) for an audio system may include at least first and second subsets of individually selectable elementary current sources for delivering analog output current contributions, a code conversion circuit for selecting elementary current sources of first and second subsets as a function of codes of a pulse code modulated (PCM) input signal. The DAC may multiply by a certain factor incoming codes of the PCM signal after their value has remained lower than a threshold for a certain period of time and for as long as their value equals or surpasses the threshold value, and may correspondingly scale and de-scale by the same factor the amplitude of the analog output current contributions produced by the elementary current sources of the two subsets.

Abstract translation: 用于音频系统的数模转换器（DAC）可以包括用于递送模拟输出电流贡献的单独可选择的基本电流源的至少第一和第二子集，用于选择第一和第二子集的基本电流源的代码转换电路， 脉冲编码调制（PCM）输入信号的代码的功能。 DAC可以在PCM信号的某一因素的输入码乘以一定时间段以后的值，并且只要它们的值等于或超过阈值，并且可以相应地缩放和解除， 按照相同因子对由两个子集的基本电流源产生的模拟输出电流贡献的幅度进行比例。

公开(公告)号：US20060164898A1

公开(公告)日：2006-07-27

申请号：US11318053

申请日：2005-12-23

Applicant: Federico Pio

Inventor： Federico Pio

IPC: G11C7/02

CPC classification number: G11C29/026 ,  G11C7/14 ,  G11C16/04 ,  G11C16/28 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50 ,  G11C29/50004

Abstract: In a semiconductor memory device, a method for obtaining at least one reference cell adapted to be exploited as a generator of a reference signal, the reference signal depending on a value of an electrical characteristic of the at least one reference cell. The method includes providing a population of auxiliary cells, operating on said population of auxiliary cells for varying a value of the electrical characteristic thereof, in such a way that the varied values are statistically distributed in a range including a value of the electrical characteristic corresponding to the reference signal, and choosing the at least one reference cell, wherein choosing includes choosing at least one auxiliary cell in the population of auxiliary cells having the value of the electrical characteristic close to the value corresponding to the reference signal with a pre-defined tolerance.

公开(公告)号：US20060161723A1

公开(公告)日：2006-07-20

申请号：US11036179

申请日：2005-01-14

Applicant: Angelo Sena ,  Agata Intini

Inventor： Angelo Sena ,  Agata Intini

IPC: G06F12/00 ,  G06F12/10

CPC classification number: G06F12/0246 ,  Y10S707/99933 ,  Y10S707/99942 ,  Y10S707/99943

Abstract: A method controls write/erase operations in a memory device, such as a NAND flash memory. The method includes dividing the memory device in physical blocks, wherein each physical block is comprised of a number of pages; considering the memory device as comprising consecutive virtual blocks, each virtual block including consecutive sectors; associating to each virtual block a virtual block number; selecting the size of the virtual blocks equal to a multiple of the size of the physical blocks; and creating a virtual-to-physical mapping table having entries. Each entry in the mapping table stores a pointer to a root node of a tree structure that links logically a set of physical blocks in the memory device.

Abstract translation: 一种方法控制诸如NAND闪存之类的存储器件中的写/擦除操作。 该方法包括在物理块中划分存储器件，其中每个物理块由多页构成; 考虑到存储器件包括连续的虚拟块，每个虚拟块包括连续的扇区; 将每个虚拟块相关联的虚拟块号; 选择虚拟块的大小等于物理块的大小的倍数; 以及创建具有条目的虚拟到物理映射表。 映射表中的每个条目存储指向树结构的根节点的指针，该树结构在逻辑上链接存储器设备中的一组物理块。

公开(公告)号：US20060120161A1

公开(公告)日：2006-06-08

申请号：US11261903

申请日：2005-10-27

Applicant: Emanuele Confalonieri ,  Nicola Del Gatto ,  Carlo Lisi ,  Marco Ferrario

Inventor： Emanuele Confalonieri ,  Nicola Del Gatto ,  Carlo Lisi ,  Marco Ferrario

IPC: G11C11/34 ,  G11C16/06

CPC classification number: G11C8/10 ,  G11C8/18 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5621

Abstract: A method and circuit for programming a multilevel memory of a flash EEPROM type having a matrix of cells grouped in memory words. The method provides for the simultaneous generation of a first programming voltage value and a second verify voltage value to bias word lines of the memory matrix during programming and verify operations, respectively, of the memory itself. A circuit implementing the above method is also provided.

Abstract translation: 一种用于编程具有分组在存储器字中的单元矩阵的闪存EEPROM类型的多级存储器的方法和电路。 该方法提供了分别在存储器本身的编程和验证操作期间同时产生第一编程电压值和第二验证电压值以偏置存储器矩阵的字线。 还提供了实现上述方法的电路。