公开(公告)号：US20050174172A1

公开(公告)日：2005-08-11

申请号：US11055925

申请日：2005-02-11

Applicant: Philippe Sirito-Olivier

Inventor： Philippe Sirito-Olivier

IPC: H03F1/30 ,  H03F1/36 ,  H03F3/45

CPC classification number: H03F3/45098 ,  H03F1/302 ,  H03F3/45538

Abstract: The method controls, in a feedback mode, a common collector or common drain amplifier, biased with a voltage applied on a bias node produced by a biasing circuit that generates a temperature compensated reference voltage from which the bias voltage applied on the bias node of the amplifier is derived. The quiescent voltage on the output node of the amplifier is made substantially independent from temperature by sensing the quiescent voltage on the output node, and adjusting the voltage applied on the bias node of the amplifier based upon the difference between the reference voltage and the sensed quiescent voltage for maintaining it constant.

Abstract translation: 该方法在反馈模式下控制公共集电极或公共漏极放大器，该偏置电压施加在由偏置电路产生的偏置电路上的电压，该偏置电路产生温度补偿的参考电压，从而施加在偏置节点上的偏置电压 派生放大器。 放大器的输出节点上的静态电压通过感测输出节点上的静态电压而基本上与温度无关，并且基于参考电压和感测到的静态之间的差异来调节施加在放大器的偏置节点上的电压 电压保持恒定。

公开(公告)号：US20050174157A1

公开(公告)日：2005-08-11

申请号：US11051137

申请日：2005-02-04

Applicant: Pietro Calo' ,  Philippe Sirito-Olivier

Inventor： Pietro Calo' ,  Philippe Sirito-Olivier

IPC: H03H7/25 ,  H03L5/00

CPC classification number: H03H7/25

Abstract: A variable attenuation network of an input voltage on an input node produces an attenuated voltage on an output node of the network, and includes a voltage divider with multiple-taps that are selectable for producing the attenuated voltage from a voltage applied on the terminals of the voltage divider. The attenuation network produces an output voltage with an attenuation ratio that is determined with at least twice the resolution of the voltage divider, because it includes at least one resistor that may be shorted by a low impedance by-pass line controlled by a switch and alternatively connected between the selected intermediate tap or any one of the two terminals of the voltage divider and the output node of the variable attenuation network, the input node of the attenuation network or a common ground node, respectively. By using more than one shortable resistor, multiple levels of resolution may be obtained.

Abstract translation: 输入节点上的输入电压的可变衰减网络在网络的输出节点上产生衰减电压，并且包括具有多个抽头的分压器，所述分压器可选择用于根据施加在所述输入节点的端子上的电压产生衰减电压 分压器 衰减网络产生具有衰减比的输出电压，该衰减比由分压器的分辨率的至少两倍决定，因为它包括至少一个电阻器，该电阻器可被由开关控制的低阻抗旁路线路短路， 连接在所选择的中间抽头或分压器的两个端子中的任一个和可变衰减网络的输出节点，衰减网络的输入节点或公共接地节点之间。 通过使用多于一个的短路电阻，可以获得多级分辨率。

公开(公告)号：US20050169089A1

公开(公告)日：2005-08-04

申请号：US11022516

申请日：2004-12-23

Applicant: Matteo Patelmo ,  Rosario Portoghese ,  Massimo Bassi ,  Stefano Scuratti

Inventor： Matteo Patelmo ,  Rosario Portoghese ,  Massimo Bassi ,  Stefano Scuratti

IPC: G11C5/00 ,  G11C29/00 ,  G11C29/50

CPC classification number: G11C29/006 ,  G11C11/41 ,  G11C29/50 ,  G11C2029/0401 ,  G11C2029/0405 ,  G11C2029/5006

Abstract: A method for locating in an array of memory cells a set of cells having a stand-by current that exceeds a certain value based on their programming state. The method includes selecting all the cells of the array of memory cells as a set of cells to be tested, and dividing the set of cells to be tested into subsets of cells, and repeatedly sensing a stand-by current absorbed by the array of memory cells after having changed the programming state of the subsets of cells. The sensed stand-by currents are compared and a subset of cells having a stand-by current exceeding the certain value are identified as a function of the comparison. The identified subset of cells is selected as a new set of cells to be tested, and the method is repeated. Otherwise, the testing stops with the just tested subset of cells having a stand-by current exceeding the certain value.

Abstract translation: 一种用于在存储器单元的阵列中定位具有基于其编程状态超过一定值的待机电流的一组单元的方法。 该方法包括将存储单元阵列的所有单元格选择为要测试的单元的集合，并将要测试的单元组划分为单元子集，并且重复地感测由存储器阵列吸收的备用电流 改变了细胞子集的编程状态后的细胞。 比较感测到的备用电流，并将具有超过特定值的待机电流的电池子集识别为比较的函数。 选择识别的细胞子集作为要测试的新的细胞集合，并重复该方法。 否则，测试停止，刚刚测试的具有超过特定值的待机电流的单元的子集。

公开(公告)号：US20050156320A1

公开(公告)日：2005-07-21

申请号：US11005832

申请日：2004-12-07

Applicant: Ubaldo Mastromatteo

Inventor： Ubaldo Mastromatteo

IPC: B81C1/00 ,  B81C3/00 ,  H01L21/60 ,  H01L21/98 ,  H01L29/40

CPC classification number: B81C1/00238 ,  B81C2201/019 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13144 ,  H01L2224/45144 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05684

Abstract: An integrated semiconductor device includes semiconductor regions and isolation regions in a first wafer of semiconductor material, and, on a second wafer of semiconductor material, interconnection structures. Plug elements provide electrical and mechanical coupling between the first and second wafers. Each plug element includes a first region coupled to the first wafer and a second region formed of a selected metal bonded with the semiconductor regions of the first wafer, forming a metal silicide.

Abstract translation: 集成半导体器件包括半导体材料的第一晶片中的半导体区域和隔离区域，以及在半导体材料的第二晶片上的互连结构。 插头元件提供第一和第二晶片之间的电气和机械耦合。 每个插头元件包括耦合到第一晶片的第一区域和由与第一晶片的半导体区域接合的选定金属形成的第二区域，形成金属硅化物。

公开(公告)号：US20050117805A1

公开(公告)日：2005-06-02

申请号：US10938426

申请日：2004-09-10

Applicant: Bruno Poutet ,  Massimiliano Barone ,  Pier Gardella ,  Danilo Pau

Inventor： Bruno Poutet ,  Massimiliano Barone ,  Pier Gardella ,  Danilo Pau

IPC: G06T9/00 ,  H04N7/26 ,  G06K9/46

CPC classification number: H04N19/90

Abstract: A digital video image is compressed by determining for a group of adjacent pixels the global error values that result from the available combinations of truncation and integration of data strings associated with the group of pixels. A combination of truncation and integration that produces a minimum global error value is identified and used to control compression of the individual strings of data associated with the group of pixels.

Abstract translation: 通过从一组相邻像素确定由与像素组相关联的数据串的截断和积分的可用组合产生的全局误差值来压缩数字视频图像。 识别产生最小全局误差值的截断和积分的组合，并用于控制与该组像素相关联的各个数据串的压缩。

公开(公告)号：US20050104659A1

公开(公告)日：2005-05-19

申请号：US10944531

申请日：2004-09-17

Applicant: Philippe Sirito-Olivier ,  Pietro Calo

Inventor： Philippe Sirito-Olivier ,  Pietro Calo

IPC: H03F3/45

CPC classification number: H03F3/45085 ,  H03F2203/45352 ,  H03F2203/45361 ,  H03F2203/45392

Abstract: A Darlington differential amplifier includes a differential pair of Darlington transistors, with each pair including a first transistor and a second transistor connected in cascade to the first transistor. The first transistor is controlled by an externally generated voltage and drives the second transistor. The first and second transistors each include first and second conducting terminals, with the first conducting terminals being connected together and forming an output node of the amplifier. A first degeneration impedance is connected between the second conduction terminals of the second transistors in the pair of Darlington transistors. A second degeneration impedance is connected between the second conduction terminals of the first transistors in the pair of Darlington transistors for reducing harmonic distortion of the amplifier.

Abstract translation: 达林顿差分放大器包括达林顿晶体管的差分对，每对包括与第一晶体管级联连接的第一晶体管和第二晶体管。 第一晶体管由外部产生的电压控制并驱动第二晶体管。 第一和第二晶体管各自包括第一和第二导电端子，其中第一导电端子连接在一起并形成放大器的输出节点。 第一退化阻抗连接在该对达林顿晶体管中的第二晶体管的第二导通端之间。 第二退化阻抗连接在该对达林顿晶体管中的第一晶体管的第二导通端之间，用于减小放大器的谐波失真。

公开(公告)号：US20050089124A1

公开(公告)日：2005-04-28

申请号：US10930733

申请日：2004-08-31

Applicant: Stefano Valle

Inventor： Stefano Valle

IPC: H04B7/01 ,  H04B17/00 ,  H04L27/06

CPC classification number: H04B7/01 ,  H04B17/336

Abstract: The Doppler spread associated to a transmission channel with a gain represented by a random process, is estimated by transmitting on the channel a digital signal (DPCCHI,Q), which comprises at least one pilot signal, which in turn comprises fields of known symbols, and estimating, on the basis of the pilot signal(DPCCHI,Q), the channel so as to generate a signal indicating the aforesaid gain. There is then detected the zero-crossing rate (η) of the aforesaid signal during a given time interval, and there is also estimated the signal-to-noise ratio (SNR) associated to the channel. The bandwidth ({circumflex over (f)}D) of the aforesaid random process is estimated according to a reference quantity (ID(2)), which comprises: a first term ({circumflex over (η)}2π2), representing an estimate ({circumflex over (η)}) of said zero-crossing rate (η); and a second term ( I N ( 2 ) - η ^ 2 ⁢ π 2 ⁢ I N ( 0 ) 2 ⁢ SNR ) , which includes said signal-to-noise ratio of the channel.

公开(公告)号：US20050085744A1

公开(公告)日：2005-04-21

申请号：US10970751

申请日：2004-10-20

Applicant: Fabrizio Beverina ,  Giorgio Palmas ,  Stefano Silvoni

Inventor： Fabrizio Beverina ,  Giorgio Palmas ,  Stefano Silvoni

IPC: A61B5/00 ,  G06F3/00 ,  G06F3/01

CPC classification number: G06F3/015 ,  A61B5/486 ,  A61B5/726 ,  A61B5/7267

Abstract: A system for developing a brain-computer interface (BCI), especially for use in rehabilitation, includes an audio-visual interface device for applying to a subject being examined stimuli eliciting event-related potentials and inducing brain reactions in said subject being examined. The system further includes an acquisition device for acquiring brain reaction signals (such as EEG traces) of the subject being examined synchronized with the stimuli and at least one processing device for processing the signals acquired via said acquisition device, The interface device, the acquisition device and the processing device comprise an integrated system. Preferably, the system uses a p300 signal as the event-related potential.

Abstract translation: 用于开发脑 - 计算机接口（BCI）的系统，特别是用于康复的系统，包括一个视听界面装置，用于向被检查的受试者施加刺激，引发事件相关电位并在所检查的受试者中引起脑反应。 该系统还包括用于获取与刺激同步的被检查对象的脑反应信号（例如EEG迹线）的采集装置和用于处理经由所述采集装置获取的信号的至少一个处理装置。接口装置，采集装置 并且处理装置包括集成系统。 优选地，系统使用p 300信号作为事件相关电位。

公开(公告)号：US20050053276A1

公开(公告)日：2005-03-10

申请号：US10893103

申请日：2004-07-15

Applicant: Salvatore Curti ,  Sebastiano Battiato ,  Emiliano Scordato ,  Marcello Tortora ,  Edoardo Ardizzone ,  Marco La Cascia

Inventor： Salvatore Curti ,  Sebastiano Battiato ,  Emiliano Scordato ,  Marcello Tortora ,  Edoardo Ardizzone ,  Marco La Cascia

IPC: G06T7/00 ,  G06K9/00

CPC classification number: G06T7/536

Abstract: A method of obtaining a depth map from a single digital image of a three-dimensional scene containing geometric objects is provided that includes the identification in the image of at least one horizontal plane or one vertical plane of the three-dimensional scene and the assignment to every point of the image forming part of the identified plane, or to each one of the identified planes, of a depth level according to its distance from, respectively, a predetermined horizontal or vertical reference straight line of the image. In particular, the identification of at least one plane includes the identification in the image of at least two vanishing lines corresponding to two parallel lines in the plane and the assignment of a depth level made in accordance with the angular coefficients of the identified vanishing lines. Also included is a completely automatic method for obtaining a depth map from a single digital image of any three-dimensional scene.

Abstract translation: 提供一种从包含几何对象的三维场景的单个数字图像获得深度图的方法，其包括三维场景的至少一个水平面或一个垂直平面的图像中的识别，以及对三维场景的分配 根据与图像的预定水平或垂直参考直线的距离，所述图像的每个点形成所识别的平面的一部分或所识别的平面中的每一个的深度级。 特别地，至少一个平面的识别包括在平面中对应于两个平行线的至少两个消失线的图像中的识别，以及根据所识别的消失线的角度系数进行的深度级的分配。 还包括用于从任何三维场景的单个数字图像获得深度图的全自动方法。

公开(公告)号：US20050040865A1

公开(公告)日：2005-02-24

申请号：US10897326

申请日：2004-07-22

Applicant: Alessandro Zafarana

Inventor： Alessandro Zafarana

IPC: H03K5/08 ,  H03K5/153

CPC classification number: H03K5/082

Abstract: A multisense-adaptive reading circuit is described, which is associated to a sense element of an interleaved DC-DC converter module. The reading circuit comprises at least a first and second current source connected to a first and second terminal of the module, connected in turn to a first and second resistive element, as well as a tracker of a current information coming from the first and second current source. Advantageously according to the invention, the reading circuit also comprises a reading mode detector effective to detect a common mode voltage value and, based on this value, to determine a reading mode being used among possible reading modes to self-adapt the reading circuit to the reading mode being used by providing convenient enabling signals to the first and second current sources and to the tracker. A multisense-self-adaptive reading method being implemented by means of that circuit is also described.

Abstract translation: 描述了与交织的DC-DC转换器模块的感测元件相关联的多重自适应读取电路。 读取电路包括至少连接到模块的第一和第二端子的第一和第二电流源，其依次连接到第一和第二电阻元件，以及来自第一和第二电流的电流信息的跟踪器 资源。 有利地，根据本发明，读取电路还包括有效检测共模电压值的读取模式检测器，并且基于该值，确定在可能的读取模式之间使用的读取模式，以将读取电路自适应到 通过向第一和第二电流源和跟踪器提供方便的启用信号来使用读取模式。 还描述了通过该电路实现的多重自适应读取方法。