公开(公告)号：US10720910B1

公开(公告)日：2020-07-21

申请号：US16653917

申请日：2019-10-15

Applicant: ASMedia Technology Inc.

Inventor： Yu-Chuan Lin

IPC: H03K5/135 ,  H03K19/20

Abstract: An eye diagram observation device is provided. The eye diagram observation device includes an eye diagram determination circuit and a clock generator. The eye diagram determination circuit obtains an eye diagram corresponding to an input signal pair based on a delayed sampling clock. The clock generator includes a voltage to time converter (VTC). The VTC generates a delayed clock based on a voltage value of an input voltage. The clock generator generates the delayed sampling clock based on the delayed clock. The eye diagram observation device may reduce power consumption and a layout area via the VTC.

公开(公告)号：US10592426B2

公开(公告)日：2020-03-17

申请号：US16038203

申请日：2018-07-18

Applicant: ASMedia Technology Inc.

Inventor： Wen-Cheng Chen

IPC: G06F12/1009 ,  G06F12/06

Abstract: A method for accessing a physical region page (PRP) list includes obtaining a PRP address of a PRP list, in which the PRP address has M bits; performing operation to the first N bits of the PRP address and the N+1 th to Mth bits of the PRP address respectively to obtain a page base address if the PRP address is within a page boundary; and performing operation to the first N bits of the PRP address and the N+1 th to Mth bits of the PRP address respectively to obtain next PRP address pointer if the PRP address reaches the page boundary. N is an integer, and M is an integer larger than N.

公开(公告)号：US10430124B1

公开(公告)日：2019-10-01

申请号：US16109777

申请日：2018-08-23

Applicant: ASMedia Technology Inc.

Inventor： Wei-Kan Hwang

IPC: G06F3/06

Abstract: A disk managing method includes: receiving a host Frame Information Structure (FIS) including multiple host logical Block Address Range Entries (LBA Range Entries) from a host; determining whether the LBA Range Entries satisfy a speed up processing condition; generating a first and a second addresses corresponding to a first and a second hard disks according to the host LBA Range Entries; and outputting a first and a second hard disk FIS to the first and the second hard disk for management. The number of first and second hard disk LBA Range Entries in the first and the second hard disk FIS are respectively half of the number of the host LBA Range Entries.

公开(公告)号：US20170293492A1

公开(公告)日：2017-10-12

申请号：US15470913

申请日：2017-03-28

Applicant: ASMedia Technology Inc.

Inventor： Chin-Lung Wu

IPC: G06F9/44 ,  G06F1/32 ,  G06F1/24

CPC classification number: G06F9/4406 ,  G06F1/24 ,  G06F1/26 ,  G06F1/3287 ,  G06F9/4411 ,  G06F9/4418

Abstract: An electronic device comprising a mainboard and a device is provided. The mainboard includes a first storage circuit, a CPU circuit and a data transmission interface circuit. The first storage circuit is configured to store a first firmware code of a basic input/output system, the CPU circuit is coupled to the first storage circuit, the CPU circuit is configured to execute the first firmware code to run the basic input/output system, and the data transmission interface circuit is coupled to the CPU circuit. The device is coupled to the data transmission interface circuit of the mainboard for providing a device function to the CPU circuit via the data transmission interface circuit. The device includes a controller, the controller includes a second storage circuit, a microcontroller and a suspend power register. An operation method of the electronic device is also provided.

公开(公告)号：US09256744B2

公开(公告)日：2016-02-09

申请号：US13858112

申请日：2013-04-08

Applicant: Ming-Wei Hsu

Inventor： Ming-Wei Hsu

IPC: G06F21/57 ,  G06F9/44 ,  G06F11/14

CPC classification number: G06F21/572 ,  G06F9/4401 ,  G06F11/1417

Abstract: A system-on-chip (SoC) and a booting method thereof are disclosed. The SoC is coupled to an external memory and includes a read only memory (ROM) and a processor. The ROM stores a first firmware image. The processor is coupled to the ROM. The processor reads the first firmware image from the ROM and verifies the state of the first firmware image. If the first firmware image is damaged, the processor reads a second firmware image from the external memory and verifies whether the second firmware image is legal. If the verification of the second firmware image succeeds, the processor reads and executes the second firmware image to perform a booting process.

Abstract translation: 公开了一种片上系统（SoC）及其引导方法。 SoC耦合到外部存储器并且包括只读存储器（ROM）和处理器。 ROM存储第一固件映像。 处理器耦合到ROM。 处理器从ROM读取第一固件映像，并验证第一固件映像的状态。 如果第一固件映像损坏，则处理器从外部存储器读取第二固件映像，并验证第二固件映像是否合法。 如果第二固件映像的验证成功，则处理器读取并执行第二固件映像以执行引导处理。

公开(公告)号：US09201614B2

公开(公告)日：2015-12-01

申请号：US14304997

申请日：2014-06-16

Applicant: ASMedia Technology Inc.

Inventor： Ming-Hui Chiu ,  Chia-Hsin Chen

IPC: G06F12/00 ,  G06F3/06 ,  G06F9/52

CPC classification number: G06F3/0689 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0659 ,  G06F9/52

Abstract: An anti-timeout method applied to a data processing system is provided. The data processing system includes a disk module. The anti-timeout method includes following steps: setting a total volume of the disk module into a plurality of virtual disk volumes, wherein each of the virtual disk volumes includes an instruction temporary storing queue for temporarily storing operating instructions corresponding to each virtual disk volume; selecting one of the instruction temporary storing queues and processing the operating instructions stored in the selected instruction temporary storing queue; calculating a continuous operating value of continuous processing of the selected instruction temporary storing queue; and selecting another one of the instruction temporary storing queues if the continuous operating value exceeds a predetermined threshold value.

Abstract translation: 提供了应用于数据处理系统的反超时方法。 数据处理系统包括一个磁盘模块。 反超时方法包括以下步骤：将磁盘模块的总体积设置为多个虚拟磁盘卷，其中每个虚拟磁盘卷包括临时存储对应于每个虚拟磁盘卷的操作指令的临时存储队列; 选择指令临时存储队列之一并处理存储在所选择的指令临时存储队列中的操作指令; 计算所选指令临时存储队列的连续处理的连续操作值; 以及如果所述连续操作值超过预定阈值，则选择所述指令临时存储队列中的另一个。

公开(公告)号：US08902955B2

公开(公告)日：2014-12-02

申请号：US13691839

申请日：2012-12-02

Applicant: Shih-Min Lin

Inventor： Shih-Min Lin

IPC: H04B1/38 ,  H04B1/44 ,  H04L25/02

CPC classification number: H04B1/44 ,  H04L25/0272 ,  H04L25/0278

Abstract: A high-definition multimedia interface (HDMI) data transceiving apparatus is disclosed. The HDMI data transceiving apparatus includes a data receiver and a data transmitter. The data transmitter includes a first impedance-providing device and a second impedance-providing device. The data transmitter has a first data transmission terminal and a second data transmission terminal. The first data transmission terminal and the second data transmission terminal are coupled to the data receiver through a first transmission line and a second transmission line, respectively. The data transmitter respectively transmits first data and second data to the data receiver. The first impedance-providing device and the second impedance-providing device absorb a reflected wave generated by the HDMI data transceiving apparatus when the first data and the second data are transmitted.

Abstract translation: 公开了一种高清多媒体接口（HDMI）数据收发装置。 HDMI数据收发装置包括数据接收器和数据发送器。 数据发射机包括第一阻抗提供装置和第二阻抗提供装置。 数据发射机具有第一数据传输终端和第二数据传输终端。 第一数据传输终端和第二数据传输终端分别通过第一传输线和第二传输线耦合到数据接收器。 数据发送器分别向数据接收机发送第一数据和第二数据。 当发送第一数据和第二数据时，第一阻抗提供装置和第二阻抗提供装置吸收由HDMI数据收发装置产生的反射波。

公开(公告)号：US20140218000A1

公开(公告)日：2014-08-07

申请号：US14159452

申请日：2014-01-21

Applicant: ASMedia Technology Inc.

Inventor： Ting-Wen SU ,  Yu-Chuan LIN

IPC: H02M1/36

CPC classification number: H02M1/36 ,  H02M3/156

Abstract: A voltage regulator circuit includes a soft start module, a pulse width modulation (PWM) module, and a voltage regulator module. The soft start module is used to receive a current feedback voltage corresponding to an input current, and compare the current feedback voltage with a comparison voltage, so as to output a switching signal. The PWM module is used to receive a clock signal and the switching signal, and determine a first PWM signal and a second PWM signal outputted by the PWM module is a high voltage level or a low voltage level according to the clock signal and the switching signal. The voltage regulator module is used to receive and adjust an output voltage corresponding to the first PWM signal and the second PWM signal.

Abstract translation: 电压调节器电路包括软启动模块，脉冲宽度调制（PWM）模块和电压调节器模块。 软启动模块用于接收对应于输入电流的电流反馈电压，并将电流反馈电压与比较电压进行比较，以输出开关信号。 PWM模块用于接收时钟信号和开关信号，并确定第一PWM信号，PWM模块输出的第二PWM信号根据时钟信号和开关信号为高电平或低电平 。 电压调节器模块用于接收和调整对应于第一PWM信号和第二PWM信号的输出电压。

公开(公告)号：US20140189189A1

公开(公告)日：2014-07-03

申请号：US14106869

申请日：2013-12-16

Applicant: ASMedia Technology Inc.

Inventor： Yang-Chen LIU ,  Hui-Yu TANG ,  Li-Feng KUO

IPC: G06F13/40

CPC classification number: G06F13/3625 ,  G06F13/385 ,  G06F13/4022

Abstract: The bandwidth allocation apparatus includes a high bandwidth arbitration module, a low bandwidth arbitration module and a multiplexer. The high bandwidth arbitration module is used to select one downstream device from the high bandwidth downstream device group for allowing uplink. The low bandwidth arbitration module is used to select one downstream device from the low bandwidth downstream device group for allowing uplink. The multiplexer selects the one of the access requests from the high bandwidth arbitration module or the low bandwidth arbitration module for allowing to uplink the access request to an upstream device. The access transmission times of the high bandwidth arbitration module and the low bandwidth arbitration module are counted respectively by a counting circuit.

Abstract translation: 带宽分配装置包括高带宽仲裁模块，低带宽仲裁模块和多路复用器。 高带宽仲裁模块用于从高带宽下游设备组中选择一个下行设备，以允许上行链路。 低带宽仲裁模块用于从低带宽下游设备组中选择一个下行设备，以允许上行链路。 多路复用器选择来自高带宽仲裁模块或低带宽仲裁模块的访问请求中的一个，以允许向上游设备上行接入请求。 高带宽仲裁模块和低带宽仲裁模块的接入传输时间分别由计数电路计数。

公开(公告)号：US20130232285A1

公开(公告)日：2013-09-05

申请号：US13778129

申请日：2013-02-27

Applicant: Wei-Yun Chang ,  Shu-Tzu Wang

Inventor： Wei-Yun Chang ,  Shu-Tzu Wang

IPC: H04L12/56

CPC classification number: H04L47/10 ,  H04L47/263

Abstract: A control method of flow control scheme and a control module thereof are provided. The provided control method includes setting a value of the transaction packets and outputting data to an external device according to the value of the transaction packets. When a not-ready transaction packet is received, the value of the transaction packets is reduced and the data is transmitted according to the value of the transaction packets.

Abstract translation: 提供了一种流量控制方案的控制方法及其控制模块。 提供的控制方法包括根据交易分组的值来设置事务分组的值并将数据输出到外部设备。 当接收到未就绪的交易分组时，减少交易分组的值，并根据交易分组的值传输数据。