公开(公告)号：US11231740B2

公开(公告)日：2022-01-25

申请号：US16269491

申请日：2019-02-06

Applicant: CREDO TECHNOLOGY GROUP LIMITED

Inventor： Fang Cai ,  Junqing Sun ,  Haoli Qian

IPC: G06F1/06 ,  H04L7/027 ,  G06F11/16 ,  G06F13/42 ,  G06F1/08 ,  G06F15/173

Abstract: Disclosed clock recovery modules provide improved performance with only limited complexity and power requirements. In one illustrative embodiment, a clock recovery method includes: oversampling a receive signal to obtain mid-symbol interval (MSI) samples and between-symbol interval (BSI) samples; processing at least the MSI samples to obtain symbol decisions; filtering the symbol decisions to obtain BSI targets; determining a timing error based on a difference between the BSI samples and the BSI targets; and deriving from the timing error a clock signal for said oversampling.

公开(公告)号：US11047205B2

公开(公告)日：2021-06-29

申请号：US15848400

申请日：2017-12-20

Applicant: Fracmaster, LLC

Inventor： Don Atencio

IPC: E21B34/02 ,  F16K3/20

Abstract: A valve seal assembly that provides for external pressure to be introduced to an energized seal of a valve, and compress the seal against a gate with enough force to block any paths where sand and chemicals would otherwise travel into valve body cavity or void. The external pressure introduced through pressure fitting makes the parts move like piston forcing the parts to compress together eliminating the machined tolerances or gaps required for the gate to be opened or closed. The compression can be provided by hydraulic pressure devices through injection ports. A separate valve seal assembly can be provided for each face of the gate and both assemblies can be activated when the fluids are flowing (open position) and an upstream valve seal assembly activated when the gate is in a closed position.

公开(公告)号：US11032103B2

公开(公告)日：2021-06-08

申请号：US16084277

申请日：2017-03-08

Applicant: Credo Technology Group Limited

Inventor： Yifei Dai ,  Haoli Qian ,  Jeff Twombly

IPC: H04L12/46 ,  H04B3/46 ,  H04L12/40 ,  H04L12/751 ,  H04L12/935

Abstract: Ethernet link extension methods and devices provide, in one illustrative embodiment, an Ethernet link extender with physical medium attachment (PMA) circuits each having a transmitter and receiver that communicate with a respective node in a sequence of communication phases. The sequence includes at least an auto-negotiation phase and a subsequent training phase, the phases occurring simultaneously for both PMA circuits. In the auto-negotiation phase, the PMA circuits operate in a pass-through mode, rendering the extender transparent to the two nodes. In the training phase, the PMA circuits operate independently, sending training frames to their respective nodes based in part on received back-channel information and locally-determined training status information. The training phases may be prolonged if needed to provide a simultaneous transition to a frame-forwarding phase of the sequence.

公开(公告)号：US11018709B2

公开(公告)日：2021-05-25

申请号：US16541094

申请日：2019-08-14

Applicant: CREDO TECHNOLOGY GROUP LIMITED

Inventor： Yattung Lam ,  Baohua Chen ,  Yifei Dai ,  William J. Brennan

IPC: H04L1/00 ,  H04B1/38 ,  H04L7/00

Abstract: Accordingly, there are disclosed herein active cables and methods that enable direct connection between different generations of network interface ports or ports supporting different standards. One illustrative embodiment is an active 1:N breakout cable that includes a unary end connector connected by electrical conductors to each of multiple split end connectors. The unary end connector is adapted to fit into a network interface port of a primary host device to provide output PAM4 electrical signals that convey a multi-lane outbound data stream to the primary host device and to accept input PAM4 electrical signals that convey multi-lane inbound data stream from the primary host device. Each of the split end connectors is adapted to fit into a network interface port of a secondary host device to provide output NRZ electrical signals that convey a split portion of the inbound data stream to that secondary host device and to accept input NRZ electrical signals that convey a split portion of the outbound data stream from that secondary host device.

公开(公告)号：US11018656B1

公开(公告)日：2021-05-25

申请号：US16691523

申请日：2019-11-21

Applicant: CREDO TECHNOLOGY GROUP LIMITED

Inventor： Junqing (Phil) Sun

IPC: H03K5/08 ,  H04L25/03 ,  H04L27/01 ,  H04L25/02 ,  H04B10/69 ,  H04B14/02 ,  H04B3/04

Abstract: An illustrative receiver includes: a decision element that derives symbol decisions from a slicer input signal; an equalizer that converts a receive signal into the slicer input signal; a summer that combines the symbol decisions with the slicer input signal to produce an error signal; and a level finder that operates on said signals to determine thresholds at which each signal has a given probability of exceeding the threshold. One illustrative level finder circuit includes: a gated comparator and an asymmetric accumulator. The gated comparator asserts a first or a second gated output signal to indicate when an input signal exceeds or falls below a threshold with a programmable condition being met. The asymmetric accumulator adapts the threshold using up steps for assertions of the first gated output signal and down steps for assertions of the second gated output signal, with the up-step size being different than the down-step size.

公开(公告)号：US10971458B2

公开(公告)日：2021-04-06

申请号：US16241481

申请日：2019-01-07

Applicant: CREDO TECHNOLOGY GROUP LIMITED

Inventor： Xike Liu

IPC: H01L23/60 ,  H01L23/00 ,  H01L23/66 ,  H01L27/02

Abstract: Illustrative impedance matching circuits and methods provide enhanced performance without meaningfully increasing cost or areal requirements. One illustrative integrated circuit embodiment includes: a pin configured to connect to a substrate pad via a solder bump having a parasitic capacitance; an inductor that couples the pin to a transmit or receive circuit; a first electrostatic discharge (ESD) protection device electrically connected to a pin end of the inductor; and a second ESD protection device electrically connected to a circuit end of the inductor, where the first ESD protection device has a first capacitance that sums with the parasitic capacitance to equal a total capacitance coupled to the circuit end of the inductor.

公开(公告)号：US10964777B2

公开(公告)日：2021-03-30

申请号：US16685875

申请日：2019-11-15

Applicant: Credo Technology Group Ltd.

Inventor： Xike Liu ,  Kuan Peng ,  Chan Ho Yeung ,  Yifei Dai ,  Lawrence Chi Fung Cheng ,  Runsheng He

IPC: H01L49/02 ,  H01F17/00 ,  H01F41/04 ,  H03B5/12

Abstract: Integrated circuits such as multi-channel receivers may require loop inductors resistant to electromagnetic field interference. Such loop inductors may include multiple non-overlapping loops each defining a corresponding dipole, the multiple dipoles summing to zero, with at least one of said loops having unequal areas. The multiple non-overlapping loops may include: a center loop defining a central magnetic dipole; and a plurality of peripheral loops equally spaced around a perimeter of the center loop, each peripheral loop defining a peripheral magnetic dipole oriented opposite the central magnetic dipole, the plurality of peripheral loops substantially canceling a field from the central magnetic dipole. The total number of loops may be odd, with particular embodiments of three, five, and seven loop designs disclosed. Single and multi-turn embodiments are provided.

公开(公告)号：US10796115B2

公开(公告)日：2020-10-06

申请号：US15355916

申请日：2016-11-18

Applicant: Jack McClintic

Inventor： Jack McClintic

IPC: G06K7/10 ,  G07C1/24

Abstract: A system of activity timing uses a radio frequency identification reader; radio frequency tags; circuit board; battery; and software to determine the elapsed time of a participant in the activity. The activity can be used for activities including, but not limited to, foot races and bicycle races.

公开(公告)号：US10787602B2

公开(公告)日：2020-09-29

申请号：US16010132

申请日：2018-06-15

Applicant: CNPC USA CORPORATION ,  BEIJING HUAMEI INC. CNPC

Inventor： Chun Zhou ,  Fuchen Liu ,  Yonggui Liu ,  Xingdong Yu

IPC: C09K8/528 ,  C09K8/04

Abstract: A shale inhibitor to improve the application of water-based drilling fluid in the shale formation rock is provided. An embodiment of the shale inhibitor is the reaction product of an amine, such as triethanolamine, and epichlorohydrin in water solution. Another embodiment of the shale inhibitor is the reaction product of triethanolamine, epichlorohydrin, and hypophosphorous acid. It is highly effective and has a better performance than most commercial products on preventing the disintegration and swelling of the shale formation.

公开(公告)号：US10771281B1

公开(公告)日：2020-09-08

申请号：US16673607

申请日：2019-11-04

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Tomas Suchy ,  Lukas Vykydal ,  Pavel Hartl ,  Marek Hustava

IPC: H04B3/00 ,  H04L12/40 ,  H04L25/02

Abstract: A semi-differential signaling technique as well as bus devices and communication systems that exploit this technique to enhance the performance of the DSI3 bus. In one embodiment, there is provided a DSI3 master device that can be coupled to a DSI3 slave device via a bus having at least a power supply conductor, a power return conductor, and a signal conductor. The master device includes: a power supply node and a power return node that respectively connect to the power supply conductor and the power return conductor to supply power to the slave device; a signal node that connects to the signal conductor; and a driver that drives the signal node relative to a reference voltage midway between voltages of the power supply node and the power return node.