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公开(公告)号：US10818608B2
公开(公告)日：2020-10-27
申请号：US15781782
申请日：2017-04-10
Applicant: Credo Technology Group Limited
IPC: H01L23/552 , H01L23/00 , H01L23/538 , H01L23/498 , H01L23/64 , H03B5/12 , H01F17/00 , H04L7/00
Abstract: Disclosed microelectronic assemblies employ an integrated interposer cage to reduce electromagnetic interference with (and from) high-frequency components. One illustrative embodiment includes: at least one IC die having drive cores for a plurality of oscillators, the IC die attached in a flip-chip configuration to a (interposer) substrate, the substrate having: multiple inductors electrically coupled to said drive cores and each enclosed within a corresponding conductive cage integrated into the substrate to reduce mutual coupling between the inductors and noise coupled through substrate. An illustrative interposer embodiment includes: upper contacts arranged to electrically connect with micro bumps on at least one IC die; metallization and dielectric layers that form multiple inductors each surrounded by bars of a conductive cage; lower contacts arranged to electrically connect with bumps on a package substrate; and a substrate with a plurality of TSVs (through-silicon vias) that electrically couple to the lower contacts. Each of the bars includes: at least one of said TSVs, at least one via through the metallization and dielectric layers, and at least one upper contact.
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公开(公告)号：US10605860B2
公开(公告)日：2020-03-31
申请号：US16044065
申请日：2018-07-24
Applicant: Credo Technology Group Limited
Inventor： Zhongnan Li , Yifei Dai
IPC: G01R31/317 , G01R31/3177 , H01L25/18 , H01L23/538 , H01L25/065 , H01L23/00
Abstract: A device includes a first die including a pseudo-random binary sequence (“PRBS”) generator that outputs test signals on parallel lanes. The device further includes a second die comprising a PRBS checker that compares at least a portion of the test signals with reference signals to identify a particular lane associated with an error.
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公开(公告)号：US20190386851A1
公开(公告)日：2019-12-19
申请号：US16084277
申请日：2017-03-08
Applicant: Credo Technology Group Limited
Inventor： Yifei Dai , Haoli Qian , Jeff Twombly
IPC: H04L12/46 , H04L12/935 , H04L12/40 , H04L12/751 , H04B3/46
Abstract: Ethernet link extension methods and devices provide, in one illustrative embodiment, an Ethernet link extender with physical medium attachment (PMA) circuits each having a transmitter and receiver that communicate with a respective node in a sequence of communication phases. The sequence includes at least an auto-negotiation phase and a subsequent training phase, the phases occurring simultaneously for both PMA circuits. In the auto-negotiation phase, the PMA circuits operate in a pass-through mode, rendering the extender transparent to the two nodes. In the training phase, the PMA circuits operate independently, sending training frames to their respective nodes based in part on received back-channel information and locally-determined training status information. The training phases may be prolonged if needed to provide a simultaneous transition to a frame-forwarding phase of the sequence.
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公开(公告)号：US20190050519A1
公开(公告)日：2019-02-14
申请号：US16026950
申请日：2018-07-03
Applicant: Credo Technology Group Limited
Inventor： Yifei Dai
IPC: G06F17/50
Abstract: A circuit design verification method suitable for use with a 2.5D transceiver device potentially having hundreds of dice mounted on an interposer. An illustrative method includes: (a) retrieving a design of a circuit that includes multiple integrated circuit dice connected via an interposer, each die having at least one contact for receiving or transmitting a digital signal conveyed by an interchip connection of the interposer, said circuit including an IO cell for each such contact; (b) obtaining a timing model for components of said circuit, the timing model accounting for propagation delays of said IO cells and propagation delays of said interchip connections; (c) performing a static timing analysis of the design using the timing model to determine data required times and data arrival times at each of said components; (d) comparing the data required times with the data arrival times to detect timing violations; and (e) reporting said timing violations.
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公开(公告)号：US20190041455A1
公开(公告)日：2019-02-07
申请号：US16044065
申请日：2018-07-24
Applicant: Credo Technology Group Limited
Inventor： Zhongnan Li , Yifei Dai
IPC: G01R31/317 , G01R31/3177 , H01L25/18 , H01L23/538
Abstract: A device includes a first die including a pseudo-random binary sequence (“PRBS”) generator that outputs test signals on parallel lanes. The device further includes a second die comprising a PRBS checker that compares at least a portion of the test signals with reference signals to identify a particular lane associated with an error.
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Patent Agency Ranking
公开(公告)号：US11451262B1
公开(公告)日：2022-09-20
申请号：US17213105
申请日：2021-03-25
Applicant: Credo Technology Group Limited
Inventor： Yifei Dai , Haoli Qian
IPC: H04B1/7183 , H04L7/033
Abstract: An illustrative spread spectrum clocking (SSC) converter includes: a deserializer to receive a data stream with an unmodulated clock; a memory coupled to the deserializer to buffer the data stream; and a serializer coupled to the memory to retransmit the data stream with a spread spectrum clock. One illustrative conversion method, which may be implemented on a monolithic integrated circuit device, includes: receiving a data stream from an external transmitter in an unmodulated clock domain; storing the data stream in a buffer; and retransmitting the data stream with a spread spectrum clock. Such converters and methods may be employed in an illustrative system having: a test module to generate test data streams and to analyze result data streams for verifying operation of one or more devices under test in a spread spectrum clock domain as the test module operates in an unmodulated clock domain.
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公开(公告)号：US11112459B2
公开(公告)日：2021-09-07
申请号：US16022989
申请日：2018-06-29
Applicant: Credo Technology Group Limited
Inventor： Haoli Qian , Yifei Dai , Ruiqing Sun
IPC: G01R31/3185
Abstract: A method for testing operation of a device under test (DUT) includes receiving an input bit stream at an input pin, the input bit stream including multiplexed test patterns for a plurality of scan chains of the DUT. The method further includes demultiplexing the multiplexed test patterns, and providing a corresponding test pattern data to each of the plurality of scan chains. The method further includes, at each of the plurality of scan chains, scanning test results from the scan chain, to produce multiplex output test data into an output bit stream.
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公开(公告)号：US20210243050A1
公开(公告)日：2021-08-05
申请号：US17237250
申请日：2021-04-22
Applicant: Credo Technology Group Limited
Inventor： Yifei Dai , Haoli Qian , Jeffey Twombly
IPC: H04L12/46 , H04B3/46 , H04L12/40 , H04L12/751 , H04L12/935
Abstract: Ethernet link extension methods and devices provide, in one illustrative embodiment, an Ethernet link extender with physical medium attachment (PMA) circuits each having a transmitter and receiver that communicate with a respective node in a sequence of communication phases. The sequence includes at least an auto-negotiation phase and a subsequent training phase, the phases occurring simultaneously for both PMA circuits. In the auto-negotiation phase, the PMA circuits operate in a pass-through mode, rendering the extender transparent to the two nodes. In the training phase, the PMA circuits operate independently, sending training frames to their respective nodes based in part on received back-channel information and locally-determined training status information. The training phases may be prolonged if needed to provide a simultaneous transition to a frame-forwarding phase of the sequence.
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公开(公告)号：US12063128B2
公开(公告)日：2024-08-13
申请号：US17237250
申请日：2021-04-22
Applicant: Credo Technology Group Limited
Inventor： Yifei Dai , Haoli Qian , Jeff Twombly
CPC classification number: H04L12/4633 , H04B3/46 , H04L12/40136 , H04L45/02 , H04L49/3054
Abstract: Ethernet link extension methods and devices provide, in one illustrative embodiment, an Ethernet link extender with physical medium attachment (PMA) circuits each having a transmitter and receiver that communicate with a respective node in a sequence of communication phases. The sequence includes at least an auto-negotiation phase and a subsequent training phase, the phases occurring simultaneously for both PMA circuits. In the auto-negotiation phase, the PMA circuits operate in a pass-through mode, rendering the extender transparent to the two nodes. In the training phase, the PMA circuits operate independently, sending training frames to their respective nodes based in part on received back-channel information and locally-determined training status information. The training phases may be prolonged if needed to provide a simultaneous transition to a frame-forwarding phase of the sequence.
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公开(公告)号：US11552873B2
公开(公告)日：2023-01-10
申请号：US16693144
申请日：2019-11-22
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Yifei Dai , Yattung Lam , Rajan Pai
Abstract: A cable, a manufacturing method, and a usage method, each facilitate product development, testing, and debugging. An illustrative embodiment of a cable manufacturing method includes: connecting a first connector plug to a first data recovery and re-modulation (DRR) device and to a first controller device; and coupling electrical signal conductors to the first DRR device to convey electrical transit signals to and from a second DRR device, the second DRR device being connected to a second connector plug. The first controller device is operable in response to a host command to initiate a debug dump by the first DRR device and to store the debug dump in a nonvolatile memory.
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