公开(公告)号：US20110085399A1

公开(公告)日：2011-04-14

申请号：US12842189

申请日：2010-07-23

Applicant: Hsu-Shun Chen ,  Cheng Hung Lee ,  Hong-Chen Cheng ,  Chung-Yi Wu

Inventor： Hsu-Shun Chen ,  Cheng Hung Lee ,  Hong-Chen Cheng ,  Chung-Yi Wu

IPC: G11C5/14

CPC classification number: G11C8/08 ,  G11C11/413

Abstract: An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current.

Abstract translation: 集成电路包括正电源节点，电流跟踪电路和包括并联耦合的多个电流路径的电流镜像电路。 多个电流通路的电流反映了电流跟踪电路的电流。 电流镜像电路被配置为响应于正电源节点上的正电源电压的减小而逐个关闭多个电流路径。 集成电路还包括接收多个电流路径的求和电流的充电节点，其中充电节点上的电压被配置为通过对和电流的充电而增加。

公开(公告)号：US07613054B2

公开(公告)日：2009-11-03

申请号：US11924437

申请日：2007-10-25

Applicant: Cheng-Hung Lee ,  Ping-Wei Wang ,  Ching-Wei Wu ,  Shu-Hsuan Lin ,  Feng-Ming Chang ,  Hung-Jen Liao

Inventor： Cheng-Hung Lee ,  Ping-Wei Wang ,  Ching-Wei Wu ,  Shu-Hsuan Lin ,  Feng-Ming Chang ,  Hung-Jen Liao

IPC: G11C7/00

CPC classification number: G11C11/412 ,  H01L27/1104

Abstract: An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells, wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device.

Abstract translation: SRAM器件包括：连接到第一本地位线的第一组存储器单元和用于访问其数据节点的第一局部互补位线; 连接到第二本地位线的第二组存储器单元和用于访问其数据节点的第二局部互补位线; 以及连接到第一和第二本地位线的全局位线和全局互补位线，用于访问第一和第二组存储器单元的数据节点，其中第一局部位线，第一局部互补位线，第二局部位线 局部位线，第二局部互补位线，全局位线和全局互补位线构成在SRAM器件中相同的金属化电平上。

公开(公告)号：US07420854B2

公开(公告)日：2008-09-02

申请号：US11493345

申请日：2006-07-26

Applicant: Cheng Hung Lee

Inventor： Cheng Hung Lee

IPC: G11C7/10

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved SRAM cell and its operating method are disclosed. The SRAM cell comprises at least four original transistors, e.g., a pair of pass-gate transistors and a pair of pull-up transistors. The SRAM cell also comprises a pair of parasitic transistors formed by making contacts to a Pwell underneath a buried insulation layer to make the Pwell a gate terminal; hence the buried insulation layer serves as a gate insulation for the parasitic transistor.

Abstract translation: 公开了一种改进的SRAM单元及其操作方法。 SRAM单元包括至少四个原始晶体管，例如一对栅极晶体管和一对上拉晶体管。 SRAM单元还包括一对寄生晶体管，其通过与掩埋绝缘层下方的P阱接触以使P阱成为栅极端子而形成; 因此掩埋绝缘层用作寄生晶体管的栅极绝缘。

公开(公告)号：US07408830B2

公开(公告)日：2008-08-05

申请号：US11593778

申请日：2006-11-07

Applicant: Cheng-Hung Lee

Inventor： Cheng-Hung Lee

IPC: G11C5/14

CPC classification number: G11C11/417 ,  G11C5/14

Abstract: This invention discloses a power supply management circuit which comprises at least one switching circuit coupled between a power supply and a power recipient circuit, and at least one voltage booster circuit coupled between a control circuit and the power recipient circuit, wherein the control circuit is configured to turn on-or-off the switching circuit, and to activate or de-activate the voltage booster circuit.

Abstract translation: 本发明公开了一种电源管理电路，其包括耦合在电源和受电电路之间的至少一个开关电路，以及耦合在控制电路和电源接收电路之间的至少一个升压电路，其中所述控制电路被配置 打开或关闭开关电路，并激活或去激活升压电路。

公开(公告)号：US20080175077A1

公开(公告)日：2008-07-24

申请号：US11654983

申请日：2007-01-18

Applicant: Cheng Hung Lee ,  Hung-Jen Liao ,  Kun-Lung Chen

Inventor： Cheng Hung Lee ,  Hung-Jen Liao ,  Kun-Lung Chen

IPC: G11C7/00

CPC classification number: G11C11/413

Abstract: A semiconductor memory is disclosed, which comprises a plurality of memory cells, at least one high voltage power supply (CVDD) line coupled to the plurality of memory cells for supplying power to the same, and at least one controllable discharging circuit coupled between the CVDD line and a complementary low voltage power supply (ground), wherein only during a write operation the controllable discharging circuit is turned on for discharging the CVDD line.

Abstract translation: 公开了一种半导体存储器，其包括多个存储器单元，耦合到用于向其供电的多个存储单元的至少一个高压电源（CVDD）线以及耦合在CVDD之间的至少一个可控放电电路 线路和互补的低压电源（接地），其中仅在写入操作期间，可控放电电路导通以排出CVDD线。

公开(公告)号：US20080025109A1

公开(公告)日：2008-01-31

申请号：US11493345

申请日：2006-07-26

Applicant: Cheng Hung Lee

Inventor： Cheng Hung Lee

IPC: G11C7/10

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved SRAM cell and its operating method are disclosed. The SRAM cell comprises at least four original transistors, e.g., a pair of pass-gate transistors and a pair of pull-up transistors. The SRAM cell also comprises a pair of parasitic transistors formed by making contacts to a Pwell underneath a buried insulation layer to make the Pwell a gate terminal; hence the buried insulation layer serves as a gate insulation for the parasitic transistor.

公开(公告)号：US08837250B2

公开(公告)日：2014-09-16

申请号：US12839490

申请日：2010-07-20

Applicant: You-Cheng Xiao ,  Hong-Chen Cheng ,  Chung-Ji Lu ,  Cheng Hung Lee ,  Jung-Hsuan Chen ,  Li-Chun Tien

Inventor： You-Cheng Xiao ,  Hong-Chen Cheng ,  Chung-Ji Lu ,  Cheng Hung Lee ,  Jung-Hsuan Chen ,  Li-Chun Tien

IPC: G11C8/10

CPC classification number: G11C8/10 ,  G11C11/413

Abstract: A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines.

Abstract translation: 字线解码器包括多个驱动器电路，设置在驱动器电路的各个输出处的多个字线以及耦合到驱动器电路并沿第一方向取向的多个主输入线。 字线解码器还包括耦合到驱动器电路并沿第一方向定向的多个次级输入线。 字线解码器还包括耦合到每个主输入线的本地解码线。 字线解码器还包括耦合到本地解码线并沿第一方向定向的解码线。 集群解码线耦合到解码线。 字线解码器被配置为基于由群集解码线和辅助输入线提供的信号来选择至少一个字线。

公开(公告)号：US08766324B2

公开(公告)日：2014-07-01

申请号：US13492469

申请日：2012-06-08

Applicant: Cheng Hung Lee

Inventor： Cheng Hung Lee

IPC: H01L27/10

CPC classification number: H01L27/0207 ,  H01L27/105

Abstract: An integrated circuit (IC) chip includes a first memory cell array block having a first metal layer containing at least two power lines, and a second memory cell array block containing at least two power lines independent of each other, wherein all the power lines on the first metal layer serving the first memory cell array block do not extend into the second memory cell array block, and all the power lines on the first metal layer serving the second memory cell array block do not extend into the first memory cell array block.

Abstract translation: 集成电路（IC）芯片包括具有包含至少两条电源线的第一金属层的第一存储单元阵列块和包含彼此独立的至少两条电源线的第二存储单元阵列块，其中所有电源线在 服务于第一存储单元阵列块的第一金属层不延伸到第二存储单元阵列块中，并且服务于第二存储单元阵列块的第一金属层上的所有电力线不延伸到第一存储单元阵列块中。

公开(公告)号：US08488396B2

公开(公告)日：2013-07-16

申请号：US12700034

申请日：2010-02-04

Applicant: Cheng Hung Lee ,  Hong-Chen Cheng ,  Chung-Ji Liu

Inventor： Cheng Hung Lee ,  Hong-Chen Cheng ,  Chung-Ji Liu

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C8/08

Abstract: A static random access memory (SRAM) macro includes a first power supply voltage and a second power supply voltage that is different from the first power supply voltage. A precharge control is connected to the second power supply voltage. The precharge control is coupled to a bit line through a bit line precharge. At least one level shifter receives a level shifter input. The level shifter converts the level shifter input having a voltage level closer to the first power supply voltage than the second power supply voltage to a level shifter output having a voltage level closer to the second power supply voltage than the first power supply voltage. The level shifter output is provided to the precharge control.

Abstract translation: 静态随机存取存储器（SRAM）宏包括与第一电源电压不同的第一电源电压和第二电源电压。 预充电控制连接到第二电源电压。 预充电控制通过位线预充电耦合到位线。 至少一个电平移位器接收电平移位器输入。 电平移位器将具有比第二电源电压更接近于第一电源电压的电压电平的电平移位器输入转换为具有比第一电源电压更接近第二电源电压的电压电平的电平移位器输出。 电平移位器输出被提供给预充电控制。

公开(公告)号：US08451669B2

公开(公告)日：2013-05-28

申请号：US13443619

申请日：2012-04-10

Applicant: Hsu-Shun Chen ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Chung-Yi Wu ,  Chih-Chieh Chiu

Inventor： Hsu-Shun Chen ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Chung-Yi Wu ,  Chih-Chieh Chiu

IPC: G11C7/00

CPC classification number: G11C7/1048 ,  G11C5/14

Abstract: In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA.

Abstract translation: 在与存储器阵列相关的一些实施例中，读出放大器（SA）使用第一电源，例如电压VDDA，而其它电路（例如，信号输出逻辑）使用第二电源，例如电压VDDB。 各种实施例将SA和一对传送装置放置在本地IO行上，并将电压保持器放置在同一存储器阵列的主IO部分。 SA，传输装置和电压保持器在适当的情况下一起工作，使得由电压VDDB提供的电路的数据逻辑与由电压VDDA提供的电路的数据逻辑相同。