公开(公告)号：US20130162335A1

公开(公告)日：2013-06-27

申请号：US13593638

申请日：2012-08-24

Applicant: Chul-Woo Kim ,  Jungmoon Kim ,  Jihwan Kim

Inventor： Chul-Woo Kim ,  Jungmoon Kim ,  Jihwan Kim

IPC: G05F1/10

CPC classification number: H02M3/073 ,  H02J3/385 ,  H02M3/07 ,  H02M2001/0012 ,  Y02E10/58

Abstract: A charge pumping apparatus includes a voltage pumping unit for pumping an input voltage, a voltage pumping control unit for controlling the voltage pumping unit according to a comparison result between the input voltage and an input criterion voltage and a comparison result between an output voltage output from the voltage pumping unit and an output criterion voltage, and an optimum power point tracking unit for tracking an optimum power point in the case of detecting that the output voltage decreases lower than the output criterion voltage, and adjusting an input impedance to change the input criterion voltage to a voltage corresponding to the optimum power point, wherein the optimum power point is a power point where an input power according to the input voltage becomes a maximum. Since the optimum power point is tracked by measuring only a voltage without a current sensor, a power loss is small.

Abstract translation: 电荷泵送装置包括用于泵浦输入电压的电压泵送单元，用于根据输入电压和输入基准电压之间的比较结果控制电压抽运单元的电压抽运控制单元，以及从 电压抽运单元和输出标准电压，以及用于在检测到输出电压降低到低于输出标准电压的情况下跟踪最佳功率点的最佳功率点跟踪单元，以及调整输入阻抗以改变输入标准 电压达到对应于最佳功率点的电压，其中最佳功率点是其中根据输入电压的输入功率变为最大值的功率点。 由于通过仅测量没有电流传感器的电压来跟踪最佳功率点，所以功率损耗小。

公开(公告)号：US20130147457A1

公开(公告)日：2013-06-13

申请号：US13495382

申请日：2012-06-13

Applicant: Chul Woo KIM ,  Jung Moon KIM

Inventor： Chul Woo KIM ,  Jung Moon KIM

IPC: G05F3/08

CPC classification number: H02M3/158 ,  H02M2001/009

Abstract: Provided is a single inductor multiple output (SIMO) direct current-to-direct current (DC/DC) converter that may perform DC/DC conversion by transferring, to output nodes, input current that is input and thereby stored in a single inductor. An output selection unit of the SIMO DC/DC converter may select, from output nodes, a first output node to be supplied with current from a driving unit, and provide output voltage of the first output node and reference voltage of the first output node to a hysteresis comparison unit. The hysteresis comparison unit may control on-time and/or inductor peak current by determining whether the output voltage of the first output node is higher than the reference voltage of the first output node by at least a first threshold, and whether the output voltage of the first output voltage is lower than the reference voltage of the first output voltage by at least a second threshold.

Abstract translation: 提供了单电感器多输出（SIMO）直流 - 直流（DC / DC）转换器，其可以通过向输出节点传送输入的输入电流并由此存储在单个电感器中来执行DC / DC转换。 SIMO DC / DC转换器的输出选择单元可以从输出节点选择要从驱动单元提供电流的第一输出节点，并且将第一输出节点的输出电压和第一输出节点的参考电压提供给 滞后比较单元。 滞后比较单元可以通过确定第一输出节点的输出电压是否高于第一输出节点的参考电压至少第一阈值来控制导通时间和/或电感峰值电流，以及是否输出电压 第一输出电压低于第一输出电压的参考电压至少第二阈值。

公开(公告)号：US08451970B2

公开(公告)日：2013-05-28

申请号：US13035093

申请日：2011-02-25

Applicant: Chul Woo Kim ,  Young Ho Kwak

Inventor： Chul Woo Kim ,  Young Ho Kwak

IPC: H03D3/24 ,  H04L7/00 ,  H04L25/40 ,  H03L7/06 ,  H03L7/00

CPC classification number: H04L7/00

Abstract: The present disclosure provides a variable delay circuit comprising a delay circuit that includes a first delay unit and a second delay unit and delays an input signal to generate an output signal; a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the input signal from the first delay unit and the second delay unit; a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increase/decrease signal; and a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.

Abstract translation: 本公开提供了一种可变延迟电路，包括延迟电路，该延迟电路包括第一延迟单元和第二延迟单元，并延迟输入信号以产生输出信号; 选择信号生成单元，其检测所述延迟电路的延迟值，并生成选择信号，以选择用于延迟来自所述第一延迟单元和所述第二延迟单元的输入信号的延迟单元; 第一控制单元，响应于延迟增减信号，控制由选择信号选择的延迟单元的延迟值; 以及第二控制单元，其控制未被选择信号选择的延迟单元的延迟值。

公开(公告)号：US08149030B2

公开(公告)日：2012-04-03

申请号：US12691023

申请日：2010-01-21

Applicant: Chul-woo Kim ,  Woo-seok Kim ,  Min-young Song ,  Jae-jin Park ,  Ji-hyun Kim ,  Young-ho Kwak

Inventor： Chul-woo Kim ,  Woo-seok Kim ,  Min-young Song ,  Jae-jin Park ,  Ji-hyun Kim ,  Young-ho Kwak

IPC: H03L7/06

CPC classification number: H03L7/23 ,  H03L7/085 ,  H03L7/0991 ,  H03L7/1075 ,  H03L2207/06 ,  H03L2207/50

Abstract: A clock generator includes a controller, a digital phase locked loop (PLL) circuit, a charge pump phase locked loop (PLL) circuit and a divider. The controller generates a division factor and a first internal clock signal in response to a low-frequency reference clock signal and a multiplication factor. The digital PLL circuit generates a second internal clock signal in response to the reference clock signal, the division factor and the first internal clock signal. The charge pump PLL circuit generates a plurality of third internal clock signals by using the second internal clock signal. The divider generates a high-frequency clock signal in response to a phase selection signal, the division factor and the third internal clock signals.

Abstract translation: 时钟发生器包括控制器，数字锁相环（PLL）电路，电荷泵锁相环（PLL）电路和分频器。 响应于低频参考时钟信号和乘法因子，控制器产生除法系数和第一内部时钟信号。 数字PLL电路响应于参考时钟信号，分频因子和第一内部时钟信号产生第二内部时钟信号。 电荷泵PLL电路通过使用第二内部时钟信号产生多个第三内部时钟信号。 分频器响应于相位选择信号，分频因子和第三内部时钟信号产生高频时钟信号。

公开(公告)号：US08067968B2

公开(公告)日：2011-11-29

申请号：US12890169

申请日：2010-09-24

Applicant: Dong-Suk Shin ,  Chul Woo Kim ,  Hyun Soo Chae

Inventor： Dong-Suk Shin ,  Chul Woo Kim ,  Hyun Soo Chae

IPC: H03L7/06

CPC classification number: H03L7/087 ,  H03L7/095

Abstract: A locking state detector includes a phase comparing unit configured to compare a reference clock signal and a feedback clock signal to generate a first phase difference distinction signal to distinguish a first phase difference range, and a second phase difference distinction signal to distinguish a second phase difference range wider than the first phase difference range, and a locking state setting unit configured to generate a locking state signal in response to the first phase difference distinction signal and the second phase difference distinction signal.

Abstract translation: 锁定状态检测器包括：相位比较单元，被配置为比较参考时钟信号和反馈时钟信号以产生第一相位差区分信号以区分第一相位差范围;以及第二相位差区别信号，以区分第二相位差 范围宽于第一相位差范围;锁定状态设置单元，被配置为响应于第一相位差识别信号和第二相位差识别信号产生锁定状态信号。

公开(公告)号：US20110228887A1

公开(公告)日：2011-09-22

申请号：US13152497

申请日：2011-06-03

Applicant: Chul-Woo KIM ,  Seok-Soo YOON ,  Young-Ho KWAK ,  In-Ho LEE ,  Ki-Hong KIM

Inventor： Chul-Woo KIM ,  Seok-Soo YOON ,  Young-Ho KWAK ,  In-Ho LEE ,  Ki-Hong KIM

IPC: H04L7/02

CPC classification number: H03L7/087 ,  H03D13/00 ,  H03L7/0891

Abstract: A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.

Abstract translation: 线性相位检测器包括响应于接收的数据信号和恢复的时钟信号而工作的上/下脉冲发生器。 相位检测器产生具有与接收的数据信号的转变和恢复的时钟信号的边沿之间的相位差成比例的脉冲宽度的上升和下降脉冲。 通过使用与相位误差成比例的线性相位检测器产生上升和下降脉冲，数据信号被有效地恢复，甚至具有显着抖动的数据信号。

公开(公告)号：US07974375B2

公开(公告)日：2011-07-05

申请号：US11843785

申请日：2007-08-23

Applicant: Chul-Woo Kim ,  Seok-Soo Yoon ,  Young-Ho Kwak ,  In-Ho Lee ,  Ki-Hong Kim

Inventor： Chul-Woo Kim ,  Seok-Soo Yoon ,  Young-Ho Kwak ,  In-Ho Lee ,  Ki-Hong Kim

IPC: H03D3/24

CPC classification number: H03L7/087 ,  H03D13/00 ,  H03L7/0891

Abstract: A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.

Abstract translation: 线性相位检测器包括响应于接收的数据信号和恢复的时钟信号而工作的上/下脉冲发生器。 相位检测器产生具有与接收的数据信号的转变和恢复的时钟信号的边沿之间的相位差成比例的脉冲宽度的上升和下降脉冲。 通过使用与相位误差成比例的线性相位检测器产生上升和下降脉冲，数据信号被有效地恢复，甚至具有显着抖动的数据信号。

公开(公告)号：US20110106469A1

公开(公告)日：2011-05-05

申请号：US12829323

申请日：2010-07-01

Applicant: Chul Woo Kim ,  Bum Sik Kim ,  Tae Hwan Chung ,  Young Kook Lee ,  Jin Hwan Jung ,  Sang Hyeon Moon ,  Sung Kyu Kim ,  Jae Won Lee

Inventor： Chul Woo Kim ,  Bum Sik Kim ,  Tae Hwan Chung ,  Young Kook Lee ,  Jin Hwan Jung ,  Sang Hyeon Moon ,  Sung Kyu Kim ,  Jae Won Lee

IPC: G01R31/00

CPC classification number: G01R31/024 ,  G01D3/08 ,  G01R31/007 ,  G01R31/2829

Abstract: The present invention relates to a circuit and method for detecting a short and a disconnection of a resolver for a Hybrid Electric Vehicle (HEV), which can accurately analyze and detect the fault code of the resolver which detects the speed of a drive motor for an HEV and the angle of a rotator for an HEV.For this, the circuit of the present invention is configured such that resistors for detection of a short/disconnection are connected between output signal terminals of a resolver which are connected to input terminals of an RDC connected to a CPU, and the CPU measures certain voltages, obtained according to voltage division by the resistors for detection of a short/disconnection and pull-up resistors connected between a power source and the output signal terminals, with reference to differential signals which are output signals provided to the RDC through the output signal terminals.

Abstract translation: 本发明涉及一种用于检测混合动力汽车（HEV）的旋转变压器的短路和断开的电路和方法，其能够精确地分析和检测解调器的故障代码，该解算器检测驱动电机的速度 HEV和HEV的旋转角度。 为此，本发明的电路被配置为使得用于检测短路/断开的电阻器连接在与连接到CPU的RDC的输入端子连接的旋转变压器的输出信号端子之间，并且CPU测量某些电压 通过电阻分压获得，用于检测连接在电源和输出信号端子之间的短路/断开和上拉电阻，用于通过输出信号端子提供给RDC的输出信号的差分信号 。

公开(公告)号：US07839190B2

公开(公告)日：2010-11-23

申请号：US12263300

申请日：2008-10-31

Applicant: Dong-Suk Shin ,  Chul Woo Kim ,  Hyun Soo Chae

Inventor： Dong-Suk Shin ,  Chul Woo Kim ,  Hyun Soo Chae

IPC: H03L7/06

CPC classification number: H03L7/087 ,  H03L7/095

Abstract: A locking state detector includes a phase comparing unit configured to compare a reference clock signal and a feedback clock signal to generate a first phase difference distinction signal to distinguish a first phase difference range, and a second phase difference distinction signal to distinguish a second phase difference range wider than the first phase difference range, and a locking state setting unit configured to generate a locking state signal in response to the first phase difference distinction signal and the second phase difference distinction signal.

Abstract translation: 锁定状态检测器包括：相位比较单元，被配置为比较参考时钟信号和反馈时钟信号以产生第一相位差区分信号以区分第一相位差范围;以及第二相位差区别信号，以区分第二相位差 范围宽于第一相位差范围;锁定状态设置单元，被配置为响应于第一相位差识别信号和第二相位差识别信号产生锁定状态信号。

公开(公告)号：US07830184B2

公开(公告)日：2010-11-09

申请号：US11659023

申请日：2005-07-27

Applicant: Chul-Woo Kim ,  Jin-Han Kim ,  Seok-Ryung Yoon ,  Young-Ho Kwak ,  Seok-Soo Yoon

Inventor： Chul-Woo Kim ,  Jin-Han Kim ,  Seok-Ryung Yoon ,  Young-Ho Kwak ,  Seok-Soo Yoon

IPC: H03B19/00

CPC classification number: G06F7/68

Abstract: A frequency multiplier is disclosed. A plurality of voltage regulators each regulate levels of voltages at first and second common nodes in response to a corresponding one of input signals from a voltage-controlled delay line. An input buffer charges the first node or discharges the second node in response to a feedback signal. An output buffer regulates a level of a voltage at an output node and outputs a frequency-multiplied clock signal and the feedback signal corresponding to the voltage level of the output node. A discharge circuit discharges the first node before a rising edge of each of the input signals from the voltage-controlled delay line is inputted. A charge circuit charges the second node before the rising edge of each of the input signals from the voltage-controlled delay line is inputted.

Abstract translation: 公开了一种倍频器。 多个电压调节器响应于来自电压控制延迟线的输入信号中的相应一个，调节第一和第二公共节点处的电压电平。 输入缓冲器对第一节点进行充电或响应于反馈信号对第二节点进行放电。 输出缓冲器调节输出节点处的电压电平，并输出倍频时钟信号和对应于输出节点电压电平的反馈信号。 在输入来自压控延迟线的每个输入信号的上升沿之前，放电电路对第一节点放电。 在输入来自压控延迟线的每个输入信号的上升沿之前，充电电路对第二节点充电。