公开(公告)号：US08442178B2

公开(公告)日：2013-05-14

申请号：US13152497

申请日：2011-06-03

申请人： Chul-Woo Kim ,  Seok-Soo Yoon ,  Young-Ho Kwak ,  In-Ho Lee ,  Ki-Hong Kim

发明人： Chul-Woo Kim ,  Seok-Soo Yoon ,  Young-Ho Kwak ,  In-Ho Lee ,  Ki-Hong Kim

IPC分类号： H03D3/24

CPC分类号： H03L7/087 ,  H03D13/00 ,  H03L7/0891

摘要： A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.

摘要翻译： 线性相位检测器包括响应于接收的数据信号和恢复的时钟信号而工作的上/下脉冲发生器。 相位检测器产生具有与接收的数据信号的转变和恢复的时钟信号的边沿之间的相位差成比例的脉冲宽度的上升和下降脉冲。 通过使用与相位误差成比例的线性相位检测器产生上升和下降脉冲，数据信号被有效地恢复，甚至具有显着抖动的数据信号。

公开(公告)号：US07974375B2

公开(公告)日：2011-07-05

申请号：US11843785

申请日：2007-08-23

申请人： Chul-Woo Kim ,  Seok-Soo Yoon ,  Young-Ho Kwak ,  In-Ho Lee ,  Ki-Hong Kim

发明人： Chul-Woo Kim ,  Seok-Soo Yoon ,  Young-Ho Kwak ,  In-Ho Lee ,  Ki-Hong Kim

IPC分类号： H03D3/24

CPC分类号： H03L7/087 ,  H03D13/00 ,  H03L7/0891

摘要： A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.

摘要翻译： 线性相位检测器包括响应于接收的数据信号和恢复的时钟信号而工作的上/下脉冲发生器。 相位检测器产生具有与接收的数据信号的转变和恢复的时钟信号的边沿之间的相位差成比例的脉冲宽度的上升和下降脉冲。 通过使用与相位误差成比例的线性相位检测器产生上升和下降脉冲，数据信号被有效地恢复，甚至具有显着抖动的数据信号。

公开(公告)号：US07639086B2

公开(公告)日：2009-12-29

申请号：US11892476

申请日：2007-08-23

申请人： In-Ho Lee ,  Seok-Soo Yoon ,  Young-Ho Kwak ,  Ki-Hong Kim ,  Chulwoo Kim

发明人： In-Ho Lee ,  Seok-Soo Yoon ,  Young-Ho Kwak ,  Ki-Hong Kim ,  Chulwoo Kim

IPC分类号： H03M7/00 ,  H03L7/06

CPC分类号： H03L7/095 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/10

摘要： A thermometer code generator includes n bit storing stages that are coupled to each other, where n is an integer greater than 1, and the n bit storing stages store a thermometer code, and are adapted to increase the stored thermometer code by 1 in synchronization with a clock signal when an up signal is active, to decrease the stored thermometer code by 1 in synchronization with the clock signal when a down signal is active, and to maintain the stored thermometer code in synchronization with the clock signal when both of the up signal and the down signal are inactive.

摘要翻译： 温度计代码发生器包括相互耦合的n位存储级，其中n是大于1的整数，并且n位存储级存储温度计代码，并且适于将存储的温度计代码增加1，与 当上行信号有效时的时钟信号，当下行信号有效时，与时钟信号同步地将所存储的温度计代码减1，并且当两个上行信号都保持存储的温度计代码与时钟信号同步时 并且下降信号无效。

公开(公告)号：US20080048904A1

公开(公告)日：2008-02-28

申请号：US11892476

申请日：2007-08-23

申请人： In-Ho Lee ,  Seok-Soo Yoon ,  Young-Ho Kwak ,  Ki-Hong Kim ,  Chulwoo Kim

发明人： In-Ho Lee ,  Seok-Soo Yoon ,  Young-Ho Kwak ,  Ki-Hong Kim ,  Chulwoo Kim

IPC分类号： H03L7/06 ,  G08C19/12

CPC分类号： H03L7/095 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/10

摘要： A thermometer code generator includes n bit storing stages that are coupled to each other, where n is an integer greater than 1, and the n bit storing stages store a thermometer code, and are adapted to increase the stored thermometer code by 1 in synchronization with a clock signal when an up signal is active, to decrease the stored thermometer code by 1 in synchronization with the clock signal when a down signal is active, and to maintain the stored thermometer code in synchronization with the clock signal when both of the up signal and the down signal are inactive.

摘要翻译： 温度计代码发生器包括相互耦合的n位存储级，其中n是大于1的整数，并且n位存储级存储温度计代码，并且适于将存储的温度计代码增加1，与 当上行信号有效时的时钟信号，当下行信号有效时，与时钟信号同步地将所存储的温度计代码减1，并且当两个上行信号都保持存储的温度计代码与时钟信号同步时 并且下降信号无效。

公开(公告)号：US20090189652A1

公开(公告)日：2009-07-30

申请号：US11659023

申请日：2005-07-27

申请人： Chul-Woo Kim ,  Jin-Han Kim ,  Seok-Ryung Yoon ,  Young-Ho Kwak ,  Seok-Soo Yoon

发明人： Chul-Woo Kim ,  Jin-Han Kim ,  Seok-Ryung Yoon ,  Young-Ho Kwak ,  Seok-Soo Yoon

IPC分类号： H03B19/00

CPC分类号： G06F7/68

摘要： A frequency multiplier is disclosed. A plurality of voltage regulators each regulate levels of voltages at first and second common nodes in response to a corresponding one of input signals from a voltage-controlled delay line. An input buffer charges the first node or discharges the second node in response to a feedback signal. An output buffer regulates a level of a voltage at an output node and outputs a frequency-multiplied clock signal and the feedback signal corresponding to the voltage level of the output node. A discharge circuit discharges the first node before a rising edge of each of the input signals from the voltage-controlled delay line is inputted. A charge circuit charges the second node before the rising edge of each of the input signals from the voltage-controlled delay line is inputted.

摘要翻译： 公开了一种倍频器。 多个电压调节器响应于来自电压控制延迟线的输入信号中的相应一个，调节第一和第二公共节点处的电压电平。 输入缓冲器对第一节点进行充电或响应于反馈信号对第二节点进行放电。 输出缓冲器调节输出节点处的电压电平，并输出倍频时钟信号和对应于输出节点电压电平的反馈信号。 在输入来自压控延迟线的每个输入信号的上升沿之前，放电电路对第一节点放电。 在输入来自压控延迟线的每个输入信号的上升沿之前，充电电路对第二节点充电。

公开(公告)号：US07830184B2

公开(公告)日：2010-11-09

申请号：US11659023

申请日：2005-07-27

申请人： Chul-Woo Kim ,  Jin-Han Kim ,  Seok-Ryung Yoon ,  Young-Ho Kwak ,  Seok-Soo Yoon

发明人： Chul-Woo Kim ,  Jin-Han Kim ,  Seok-Ryung Yoon ,  Young-Ho Kwak ,  Seok-Soo Yoon

IPC分类号： H03B19/00

CPC分类号： G06F7/68

摘要： A frequency multiplier is disclosed. A plurality of voltage regulators each regulate levels of voltages at first and second common nodes in response to a corresponding one of input signals from a voltage-controlled delay line. An input buffer charges the first node or discharges the second node in response to a feedback signal. An output buffer regulates a level of a voltage at an output node and outputs a frequency-multiplied clock signal and the feedback signal corresponding to the voltage level of the output node. A discharge circuit discharges the first node before a rising edge of each of the input signals from the voltage-controlled delay line is inputted. A charge circuit charges the second node before the rising edge of each of the input signals from the voltage-controlled delay line is inputted.

摘要翻译： 公开了一种倍频器。 多个电压调节器响应于来自电压控制延迟线的输入信号中的相应一个，调节第一和第二公共节点处的电压电平。 输入缓冲器对第一节点进行充电或响应于反馈信号对第二节点进行放电。 输出缓冲器调节输出节点处的电压电平，并输出倍频时钟信号和对应于输出节点电压电平的反馈信号。 在输入来自压控延迟线的每个输入信号的上升沿之前，放电电路对第一节点放电。 在输入来自压控延迟线的每个输入信号的上升沿之前，充电电路对第二节点充电。

公开(公告)号：US07106117B2

公开(公告)日：2006-09-12

申请号：US10910644

申请日：2004-08-04

申请人： Gun-Ok Jung ,  Jin-Han Kim ,  Sung-Bae Park ,  Chul-Woo Kim ,  Seok-Soo Yoon ,  Seok-Ryoung Yoon

发明人： Gun-Ok Jung ,  Jin-Han Kim ,  Sung-Bae Park ,  Chul-Woo Kim ,  Seok-Soo Yoon ,  Seok-Ryoung Yoon

IPC分类号： H03H11/26

CPC分类号： H03K5/133 ,  H03K5/135 ,  H03K2005/00156 ,  H03K2005/00286

摘要： A device which may be configured to generate delayed clock signals by a specified phase difference, which may include a clock generator circuit for generating at least one clock signal, a delayed clock signal generator for delaying the at least one clock signal, a phase detect circuit for generating a selecting signal based on the amount of phase delay detected according to a half-cycle (π), and in comparison with the clock signal, a phase interpolation circuit for controlling the delay time of the delayed clock signals and interpolating the delayed clock signals, and a selecting circuit which outputs the delayed clock signal delayed by a specified phase difference.

摘要翻译： 一种可被配置为通过指定的相位差产生延迟的时钟信号的装置，其可以包括用于产生至少一个时钟信号的时钟发生器电路，用于延迟所述至少一个时钟信号的延迟时钟信号发生器，相位检测电路 用于基于根据半周期（pi）检测到的相位延迟量来生成选择信号，并且与时钟信号相比，相位插值电路用于控制延迟的时钟信号的延迟时间并内插延迟的时钟 信号，以及输出延迟了指定相位差的延迟时钟信号的选择电路。

公开(公告)号：US20050052211A1

公开(公告)日：2005-03-10

申请号：US10910644

申请日：2004-08-04

申请人： Gun-Ok Jung ,  Jin-Han Kim ,  Sung-Bae Park ,  Chul-Woo Kim ,  Seok-Soo Yoon ,  Seok-Ryoung Yoon

发明人： Gun-Ok Jung ,  Jin-Han Kim ,  Sung-Bae Park ,  Chul-Woo Kim ,  Seok-Soo Yoon ,  Seok-Ryoung Yoon

IPC分类号： G06F1/06 ,  H03H11/26 ,  H03K5/00 ,  H03K5/05 ,  H03K5/13 ,  H03K5/135 ,  H03K5/15 ,  H03K5/26 ,  H03L7/081 ,  H04L7/02

CPC分类号： H03K5/133 ,  H03K5/135 ,  H03K2005/00156 ,  H03K2005/00286

摘要： A device which may be configured to generate delayed clock signals by a specified phase difference, which may include a clock generator circuit for generating at least one clock signal, a delayed clock signal generator for delaying the at least one clock signal, a phase detect circuit for generating a selecting signal based on the amount of phase delay detected according to a half-cycle (π), and in comparison with the clock signal, a phase interpolation circuit for controlling the delay time of the delayed clock signals and interpolating the delayed clock signals, and a selecting circuit which outputs the delayed clock signal delayed by a specified phase difference.

摘要翻译： 一种可以被配置为通过指定的相位差产生延迟的时钟信号的装置，其可以包括用于产生至少一个时钟信号的时钟发生器电路，用于延迟所述至少一个时钟信号的延迟时钟信号发生器，相位检测电路 用于基于根据半周期（pi）检测到的相位延迟量来生成选择信号，并且与时钟信号相比，相位插值电路用于控制延迟的时钟信号的延迟时间并内插延迟的时钟 信号，以及输出延迟了指定相位差的延迟时钟信号的选择电路。