公开(公告)号：US20100325326A1

公开(公告)日：2010-12-23

申请号：US12758274

申请日：2010-04-12

Applicant: CHUNG-CHING HUANG ,  YEH CHO ,  JIA-HUNG WANG ,  KUO-HAN CHANG

Inventor： CHUNG-CHING HUANG ,  YEH CHO ,  JIA-HUNG WANG ,  KUO-HAN CHANG

IPC: G06F13/40 ,  G06F13/28 ,  G06F12/00

CPC classification number: G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: A device information management system for managing device information of various peripheral devices is disclosed. The system includes a central processing unit, a logic controller connected with the central processing unit, a first device connected with the logic controller, wherein the first device has a device information stored in a memory unit for identifying the first device, and a second device connected with the first device, wherein the first device outputs an access command to the second device and the second device accesses the memory unit to retrieve the device information of the first device according to the access command.

Abstract translation: 公开了一种用于管理各种外围设备的设备信息的设备信息管理系统。 该系统包括中央处理单元，与中央处理单元连接的逻辑控制器，与逻辑控制器连接的第一设备，其中第一设备具有存储在用于识别第一设备的存储器单元中的设备信息，以及第二设备 与所述第一设备连接，其中所述第一设备向所述第二设备输出访问命令，并且所述第二设备访问所述存储器单元以根据所述访问命令检索所述第一设备的设备信息。

公开(公告)号：US20080222345A1

公开(公告)日：2008-09-11

申请号：US11945311

申请日：2007-11-27

Applicant: Wen-Juin Huang ,  Chung-Ching Huang ,  Chien-Ping Chung

Inventor： Wen-Juin Huang ,  Chung-Ching Huang ,  Chien-Ping Chung

IPC: G06F12/00

CPC classification number: G06F12/1416 ,  G06F9/30003 ,  G06F2212/2022

Abstract: A memory access method for accessing data from a non-volatile memory in a south bridge is provided. Memory access is performed under a system management mode (SMM). Under the protection of the SMM mode, the desired memory address is not altered by an interrupt handler, therefore memory data is accessed correctly.

Abstract translation: 提供了一种用于从南桥的非易失性存储器访问数据的存储器访问方法。 在系统管理模式（SMM）下执行内存访问。 在SMM模式的保护下，所需的存储器地址不会被中断处理程序改变，因此存储器数据被正确访问。

公开(公告)号：US20080018651A1

公开(公告)日：2008-01-24

申请号：US11522900

申请日：2006-09-19

Applicant: Wen-Juin Huang ,  Chung-Ching Huang ,  Hao-Lin Lin

Inventor： Wen-Juin Huang ,  Chung-Ching Huang ,  Hao-Lin Lin

IPC: G06F15/00

CPC classification number: G06F11/0787 ,  G06F11/0706

Abstract: A method for capturing an image data from a frame buffer of a computer system takes advantage of a system management interrupt service optionally triggered. If a storage unit functions normally when the computer system fails to work normally, store the image data in the frame buffer into the storage unit. Otherwise, temporarily store the image data in a buffer unit, and then store it in a NVRAM. Then restart the storage unit and restore the image data in the buffer unit into the storage unit. At last, restart the computer system.

Abstract translation: 用于从计算机系统的帧缓冲器捕获图像数据的方法利用可选地触发的系统管理中断服务。 如果计算机系统无法正常工作时存储单元正常工作，则将帧缓冲区中的图像数据存储到存储单元中。 否则，将图像数据临时存储在缓冲单元中，然后将其存储在NVRAM中。 然后重新启动存储单元，并将缓冲单元中的图像数据恢复到存储单元中。 最后重新启动计算机系统。

公开(公告)号：US20080010476A1

公开(公告)日：2008-01-10

申请号：US11707966

申请日：2007-02-20

Applicant: Wen-Juin Huang ,  Chung-Ching Huang ,  Jui-Ming Wei

Inventor： Wen-Juin Huang ,  Chung-Ching Huang ,  Jui-Ming Wei

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

Abstract: For saving power of a central processing unit at a C3 power level upon processing a bus master request from a peripheral device, an arbitrator is disabled from transmitting any request to the central processing unit at the C3 power level. Afterwards, in response to a bus master request, the central processing unit is switched from the C3 power level to a transitional C0 power level while keeping the arbitrator disabled, and then switched from the transitional C0 power level to a C2 power level while enabling the arbitrator to process the bus master request.

Abstract translation: 为了在从外围设备处理总线主机请求时以C3功率电平节省中央处理单元的功率，仲裁器被禁止在C3功率电平向中央处理单元发送任何请求。 然后，响应于总线主机请求，中央处理单元从C3功率电平切换到过渡C0功率电平，同时保持仲裁器禁用，然后从过渡C0功率电平切换到C2功率电平，同时使能 仲裁员处理总线主机请求。

公开(公告)号：US20050120154A1

公开(公告)日：2005-06-02

申请号：US11000300

申请日：2004-11-30

Applicant: Tony Ho ,  Chung-Ching Huang ,  Norman Chung

Inventor： Tony Ho ,  Chung-Ching Huang ,  Norman Chung

IPC: G06F13/24

CPC classification number: G06F13/24 ,  Y02D10/14

Abstract: An interruption control system includes an interruption message generator, a stop clock control module and an interruption status indicating path. The interruption message generator is used for decoding and identifying a message signaled interrupt (MSI) issued by a first peripheral device or a second peripheral device when interruption is to be conducted, and generates an interruption status indicating message in response to the message signaled interrupt (MSI). The stop clock control module is coupled to the interruption message generator and the CPU and de-asserts a stop clock signal that is previously asserted to have the CPU enter a power-saving state to have the CPU deactivate the power-saving state in response to the interruption status indicating message. The interruption status indicating path is used for transmitting the interruption status indicating message.

Abstract translation: 中断控制系统包括中断消息发生器，停止时钟控制模块和中断状态指示路径。 所述中断消息发生器用于在进行中断时解码和识别由第一外围设备或第二外围设备发出的消息信号中断（MSI），并响应于消息信号中断产生中断状态指示消息（ MSI）。 停止时钟控制模块耦合到中断消息发生器和CPU，并且取消断言先前断言的停止时钟信号，以使CPU进入省电状态，以使CPU能够响应于CPU 中断状态指示消息。 中断状态指示路径用于发送中断状态指示消息。

公开(公告)号：US20050114723A1

公开(公告)日：2005-05-26

申请号：US10980443

申请日：2004-11-03

Applicant: Tony Ho ,  Chung-Ching Huang ,  Norman Chung

Inventor： Tony Ho ,  Chung-Ching Huang ,  Norman Chung

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3215

Abstract: An interruption control system includes a first input/output interruption controller, a second input/output interruption controller and an interruption status indicating path. The first input/output interruption controller is coupled to a first peripheral device and a south bridge chip, and issues a wake-up signal to the south bridge chip in response to a first interrupt signal asserted by the first peripheral device so as to deactivate a power-saving state of the computer system. The second input/output interruption controller is coupled to a second peripheral device and a north bridge chip, and in response to a second interrupt signal asserted by the second peripheral device, generates a message signaled interrupt. The interruption status indicating path transmits the message signaled interrupt from the second input/output interruption controller to the south bridge chip to have the south bridge chip deactivate the power-saving state of the computer system in response to the message signaled interrupt.

Abstract translation: 中断控制系统包括第一输入/输出中断控制器，第二输入/输出中断控制器和中断状态指示路径。 第一输入/输出中断控制器耦合到第一外围设备和南桥芯片，并且响应于由第一外围设备断言的第一中断信号向南桥芯片发出唤醒信号， 计算机系统的省电状态。 第二输入/输出中断控制器耦合到第二外围设备和北桥芯片，并且响应于由第二外围设备断言的第二中断信号，产生消息信号中断。 中断状态指示路径将消息信号中断从第二输入/输出中断控制器发送到南桥芯片，以使南桥芯片响应于消息信号中断而使计算机系统的省电状态停止。