公开(公告)号：US20140047150A1

公开(公告)日：2014-02-13

申请号：US13570874

申请日：2012-08-09

Applicant: Bryan D. Marietta ,  Gary L. Whisenhunt ,  Kumar K. Gala ,  David B. Kramer

Inventor： Bryan D. Marietta ,  Gary L. Whisenhunt ,  Kumar K. Gala ,  David B. Kramer

IPC: G06F13/26

CPC classification number: G06F13/26 ,  G06F9/45533 ,  G06F9/5077 ,  G06F13/14 ,  G06F13/24

Abstract: A method and circuit for a data processing system (200) provide a processor-based partitioned priority blocking mechanism by storing interrupt identifiers, partition identifiers, thread identifiers, and priority levels associated with accepted interrupt requests in special purpose registers (35-38) located at the processor core (26) to enable quick and efficient interrupt priority blocking on a partition basis.

Abstract translation: 用于数据处理系统（200）的方法和电路通过将所接收的中断请求相关联的中断标识符，分区标识符，线程标识符和优先级级别存储在位于专用寄存器（35-38）中来提供基于处理器的分区优先级阻塞机制 在处理器核心（26）上，以便在分区的基础上实现快速有效的中断优先级阻塞。

公开(公告)号：US20130275989A1

公开(公告)日：2013-10-17

申请号：US13445582

申请日：2012-04-12

Applicant: Kun Xu ,  David B. Kramer ,  Marie J. Sullivan

Inventor： Kun Xu ,  David B. Kramer ,  Marie J. Sullivan

IPC: G06F9/50

CPC classification number: G06F9/5022 ,  G06F11/1438 ,  G06F11/1479

Abstract: An integrated circuit device includes a processor core, and a controller. The processor core issues a command intended for a first thread of a plurality of threads. The controller initiates de-allocates hardware resources of the controller that are allocated to the first thread during a thread reset process for the first thread, returns a specified value to the processor core in response to the first command intended for the first thread during the thread reset process, drops responses intended for the first thread from other devices during the thread reset process, completes the thread reset process in response to a determination that all expected responses intended for the first thread have been either received or dropped, and continues to issue requests to other devices in response to commands from other threads of the plurality of threads and processing corresponding responses during the thread reset process.

Abstract translation: 集成电路装置包括处理器核心和控制器。 处理器核心发出用于多个线程的第一线程的命令。 在针对第一线程的线程复位过程期间，控制器启动对分配给第一线程的控制器的硬件资源的分配，响应于在线程期间针对第一线程的第一命令，将指定的值返回到处理器核心 复位过程在线程重置过程期间将针对其他设备的第一个线程的响应丢弃，响应于所有预期针对第一个线程的预期响应已被接收或丢弃的确定而完成线程重置过程，并且继续发出请求 响应于来自多个线程的其他线程的命令并且在线程重置过程期间处理对应的响应而发送到其他设备。

公开(公告)号：US08560782B2

公开(公告)日：2013-10-15

申请号：US12563902

申请日：2009-09-21

Applicant: Bryan D. Marietta ,  David B. Kramer ,  Gregory B. Shippen

Inventor： Bryan D. Marietta ,  David B. Kramer ,  Gregory B. Shippen

IPC: G06F12/00

CPC classification number: G06F12/1433 ,  G06F21/805

Abstract: In a data processing system having a plurality of resources and plurality of partitions, each partition including one or more resources of the plurality of resources, a method includes receiving an access request to a target resource of the plurality of resources; using a first set of transaction attributes of the access request to determine a partition identifier for the access request in which the partition identifier indicates a partition of the plurality of partitions which includes the target resource; using the partition identifier to determine access permissions for the partition indicated by the partition identifier; and based on the access permissions, determining whether or not the access request is permitted.

Abstract translation: 在具有多个资源和多个分区的数据处理系统中，每个分区包括所述多个资源中的一个或多个资源，所述方法包括：向所述多个资源中的目标资源接收访问请求; 使用所述访问请求的第一组事务属性来确定所述访问请求的分区标识符，其中所述分区标识符指示包括所述目标资源的所述多个分区的分区; 使用分区标识符来确定由分区标识符指示的分区的访问权限; 并且基于访问权限，确定是否允许访问请求。

公开(公告)号：US20130138841A1

公开(公告)日：2013-05-30

申请号：US13307271

申请日：2011-11-30

Applicant: KUN XU ,  TOMMI M. JOKINEN ,  DAVID B. KRAMER

Inventor： KUN XU ,  TOMMI M. JOKINEN ,  DAVID B. KRAMER

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A method includes generating, by a first software process of the data processing system, a source partition descriptor for a DMA job which requires access to a first partition of a memory which is assigned to a second software process of the data processing system and not assigned to the first software process. The source partition descriptor comprises a partition identifier which identifies the first partition of the memory. The DMA unit receives the source partition descriptor and generates a destination partition descriptor for the DMA job. Generating the destination partition descriptor includes translating, by the DMA unit, the partition identifier to a buffer pool identifier which identifies a physical address within the first partition of the memory which is assigned to the second software process; and storing, by the DMA unit, the buffer pool identifier in the destination partition descriptor.

Abstract translation: 一种方法包括通过数据处理系统的第一软件过程生成用于DMA作业的源分区描述符，其需要访问分配给数据处理系统的第二软件处理并且未分配的存储器的第一分区 到第一个软件过程。 源分区描述符包括标识存储器的第一分区的分区标识符。 DMA单元接收源分区描述符，并为DMA作业生成目标分区描述符。 生成目的地分区描述符包括由DMA单元将分区标识符转换为标识分配给第二软件进程的存储器的第一分区内的物理地址的缓冲池标识符; 并且由DMA单元将缓冲池标识符存储在目的地分区描述符中。

公开(公告)号：US20120331187A1

公开(公告)日：2012-12-27

申请号：US13168331

申请日：2011-06-24

Applicant: Kun Xu ,  Tommi M. Jokinen ,  David B. Kramer

Inventor： Kun Xu ,  Tommi M. Jokinen ,  David B. Kramer

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A method for controlling bandwidth in a direct memory access (DMA) unit of a computer processing system, the method comprising: assigning a DMA job to a selected DMA engine; starting a source timer; and issuing a request to read a next section of data for the DMA job. If a sufficient amount of the data was not obtained, allowing the DMA engine to wait until the source timer reaches a specified value before continuing to read additional data for the DMA job.

Abstract translation: 一种用于控制计算机处理系统的直接存储器访问（DMA）单元中的带宽的方法，所述方法包括：将DMA作业分配给所选择的DMA引擎; 启动源计时器; 并发出读取DMA作业的下一个数据部分的请求。 如果未获得足够数量的数据，则允许DMA引擎等待，直到源定时器达到指定值，然后再继续读取DMA作业的其他数据。

公开(公告)号：US20110238941A1

公开(公告)日：2011-09-29

申请号：US12748617

申请日：2010-03-29

Applicant: Kun Xu ,  David B. Kramer

Inventor： Kun Xu ,  David B. Kramer

IPC: G06F12/00

CPC classification number: G06F13/1689 ,  G06F12/0215

Abstract: A data processing system employs an improved arbitration process in selecting pending memory access requests received from the one or more processor cores for servicing by the memory. The arbitration process uses memory timing and state information pertaining both to memory access requests already submitted to the memory for servicing and to the pending memory access requests which have not yet been selected for servicing by the memory. The memory timing and state information may be predicted memory timing and state information; that is, the component of the data processing system that implements the improved scheduling algorithm may not be able to determine the exact point in time at which a memory controller initiates a memory access for a corresponding memory access request and thus the component maintains information that estimates or otherwise predicts the particular state of the memory at any given time.

Abstract translation: 数据处理系统采用改进的仲裁过程来选择从一个或多个处理器核心接收到的待存储器访问请求，以便由存储器进行服务。 仲裁过程使用与已经提交到存储器进行服务的存储器访问请求有关的存储器定时和状态信息以及尚未被存储器维护的未决存储器访问请求。 存储器定时和状态信息可以是预测的存储器定时和状态信息; 也就是说，实现改进的调度算法的数据处理系统的组件可能不能够确定存储器控制器针对相应的存储器访问请求启动存储器访问的确切时间点，因此该组件保持估计的信息 或以其他方式预测在任何给定时间的存储器的特定状态。

公开(公告)号：US20110072220A1

公开(公告)日：2011-03-24

申请号：US12563902

申请日：2009-09-21

Applicant: Bryan D. Marietta ,  David B. Kramer ,  Gregory B. Shippen

Inventor： Bryan D. Marietta ,  David B. Kramer ,  Gregory B. Shippen

IPC: G06F12/00

CPC classification number: G06F12/1433 ,  G06F21/805

Abstract: In a data processing system having a plurality of resources and plurality of partitions, each partition including one or more resources of the plurality of resources, a method includes receiving an access request to a target resource of the plurality of resources; using a first set of transaction attributes of the access request to determine a partition identifier for the access request in which the partition identifier indicates a partition of the plurality of partitions which includes the target resource; using the partition identifier to determine access permissions for the partition indicated by the partition identifier; and based on the access permissions, determining whether or not the access request is permitted.

Abstract translation: 在具有多个资源和多个分区的数据处理系统中，每个分区包括所述多个资源中的一个或多个资源，所述方法包括：向所述多个资源中的目标资源接收访问请求; 使用所述访问请求的第一组事务属性来确定所述访问请求的分区标识符，其中所述分区标识符指示包括所述目标资源的所述多个分区的分区; 使用分区标识符来确定由分区标识符指示的分区的访问权限; 并且基于访问权限，确定是否允许访问请求。

公开(公告)号：US07477636B2

公开(公告)日：2009-01-13

申请号：US10722933

申请日：2003-11-26

Applicant: Asif Q. Khan ,  David B. Kramer ,  David P. Sonnier

Inventor： Asif Q. Khan ,  David B. Kramer ,  David P. Sonnier

IPC: H04B7/212

CPC classification number: H04L47/2441 ,  H04L47/22 ,  H04L47/50 ,  H04L47/522 ,  H04L47/568 ,  H04L47/58 ,  H04L2012/5679

Abstract: A processor includes a scheduler operative to schedule data blocks for transmission from a plurality of queues or other transmission elements, utilizing at least a first table and a second table. The first table may comprise at least first and second first-in first-out (FIFO) lists of entries corresponding to transmission elements for which data blocks are to be scheduled in accordance with a first scheduling algorithm, such as a weighted fair queuing scheduling algorithm. The scheduler maintains a first table pointer identifying at least one of the first and second lists of the first table as having priority over the other of the first and second lists of the first table. The second table includes a plurality of entries corresponding to transmission elements for which data blocks are to be scheduled in accordance with a second scheduling algorithm, such as a constant bit rate or variable bit rate scheduling algorithm.

Abstract translation: 处理器包括调度器，其利用至少第一表和第二表来调度用于从多个队列或其他传输元件传输的数据块。 第一表可以包括对应于根据第一调度算法（例如加权公平排队调度算法）对数据块进行调度的传输元件的条目的至少第一和第二先进先出（FIFO）列表 。 调度器维护第一表指针，其将第一表的第一列表和第二列表中的至少一个列表标识为优先于第一表的第一和第二列表中的另一列。 第二表包括对应于根据诸如恒定比特率或可变比特率调度算法的第二调度算法对其数据块进行调度的传输元件的多个条目。

公开(公告)号：US07443793B2

公开(公告)日：2008-10-28

申请号：US10085219

申请日：2002-02-28

Applicant: David B. Kramer ,  David P. Sonnier

Inventor： David B. Kramer ,  David P. Sonnier

IPC: H04J3/14

CPC classification number: H04L47/22 ,  H04L47/50 ,  H04L2012/5675

Abstract: A processor includes scheduling circuitry for scheduling data blocks for transmission from multiple transmission elements, and traffic shaping circuitry coupled to the scheduling circuitry and operative to establish a traffic shaping requirement for the transmission of the data blocks from the transmission elements. The scheduling circuitry is configured for utilization of at least one time slot table which includes multiple locations, each corresponding to a transmission time slot. The scheduling circuitry is operative in conjunction with the time slot table to schedule the data blocks for transmission in a manner that substantially maintains the traffic shaping requirement established by the traffic shaping circuitry even in the presence of collisions between requests from the transmission elements for each of one or more of the time slots. In an illustrative embodiment, the scheduling circuitry utilizes a transmission element linking mechanism in conjunction with a set of pointers to accommodate multiple transmission elements which request the same time slot.

Abstract translation: 处理器包括用于调度用于从多个传输元件传输的数据块的调度电路，以及耦合到调度电路的业务整形电路，并用于建立用于从传输元件传输数据块的流量整形要求。 调度电路被配置为利用至少一个时隙表，其包括多个位置，每个对应于传输时隙。 调度电路与时隙表一起工作，以便以基本上维持流量整形电路建立的流量整形需求的方式调度数据块，即使在来自传输元件的请求之间存在冲突， 一个或多个时隙。 在说明性实施例中，调度电路利用传输元件链接机制结合一组指针来适应请求相同时隙的多个传输元件。

公开(公告)号：US07224681B2

公开(公告)日：2007-05-29

申请号：US10085223

申请日：2002-02-28

Applicant: David B. Kramer ,  David P. Sonnier ,  Leslie Zsohar

Inventor： David B. Kramer ,  David P. Sonnier ,  Leslie Zsohar

IPC: H04B7/212 ,  H04L12/28 ,  H04L12/56

CPC classification number: H04L49/90 ,  H04L47/50 ,  H04L47/521 ,  H04L49/901 ,  H04L49/9063 ,  H04L49/9073

Abstract: A processor includes scheduling circuitry for scheduling data blocks for transmission from a plurality of transmission elements. The scheduling circuitry has at least one time slot table accessible thereto, and is configured for utilization of the time slot table in scheduling the data blocks for transmission. The time slot table includes a plurality of locations, with each of the locations corresponding to a transmission time slot and being configurable for storing identifiers of at least two of the transmission elements. In an illustrative embodiment, a given one of the locations in the time slot table stores in a first portion thereof an identifier of a first one of the transmission elements that has requested transmission of a block of data in the corresponding time slot, and stores in a second portion thereof an identifier of a second one of the transmission elements that has requested transmission of a block of data in the corresponding time slot. Furthermore, additional transmission elements generating colliding requests for the given location can be linked between the first and second transmission elements using a linking mechanism. The use of multi-entry time slot table locations to accommodate collisions between transmission element requests considerably facilitates the maintenance of desired traffic shaping requirements.

Abstract translation: 处理器包括用于调度用于从多个传输元件传输的数据块的调度电路。 调度电路具有可访问的至少一个时隙表，并且被配置为在调度用于发送的数据块时利用该时隙表。 时隙表包括多个位置，其中每个位置对应于传输时隙，并且可配置为存储至少两个传输元件的标识符。 在说明性实施例中，时隙表中的给定一个位置在其第一部分中存储已经请求在相应时隙中发送数据块的第一个传输元件的标识符，并存储在 其第二部分是已经请求在相应时隙中传输数据块的传输元件中的第二个的标识符。 此外，产生对给定位置的冲突请求的附加传输元件可以使用链接机构在第一和第二传输元件之间链接。 使用多入口时隙表位置来适应传输元件请求之间的冲突大大有助于维持所需的流量整形要求。