公开(公告)号：US06204126B1

公开(公告)日：2001-03-20

申请号：US09506930

申请日：2000-02-18

申请人： Chia-Ta Hsieh ,  Tai-Fen Lin ,  Wen-Ting Chu ,  Chuang-Ke Yeh ,  Hung-Cheng Sung ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Tai-Fen Lin ,  Wen-Ting Chu ,  Chuang-Ke Yeh ,  Hung-Cheng Sung ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to isolation, to source and to word line. This multi-self-aligned structure, which provides the maximum shrinkage of the cell that is possible, is also disclosed. The multi-self-alignment is accomplished by first defining the floating gate at the same time the trench isolation is formed, and then self-aligning the source to the floating gate by using a nitride layer as a hard mask in place of the traditional polyoxide, and finally forming a polysilicon spacer to align the word line to the floating gate. Furthermore, a thin floating gate is used to form a thin and sharp poly tip through the use of a “smiling effect” to advantage. The tip substantially decreases the coupling ratio of the floating gate to the word line for fast erasing speed, while at the same time increasing the coupling of the source to the floating gate with the attendant increase in the programming speed of the split gate flash memory cell.

摘要翻译： 公开了一种用于形成分离栅闪存单元的方法，其中单元的浮置栅极自对准到隔离，源极和字线。 还公开了提供可能的电池的最大收缩率的多自对准结构。 通过首先在形成沟槽隔离的同时首先定义浮栅，然后通过使用氮化物层作为硬掩模来代替传统的多晶氧体来将源自对准到浮栅来实现多自对准 ，并最终形成多晶硅间隔物以将字线对准浮动栅极。 此外，通过使用“微笑效果”，薄的浮动门用于形成薄而尖的多头尖端。 尖端大大降低了浮动栅极与字线的耦合比，以实现快速擦除速度，同时增加了源极与浮栅的耦合，伴随着分流栅闪存单元的编程速度的增加 。

公开(公告)号：US06174772B1

公开(公告)日：2001-01-16

申请号：US09347548

申请日：1999-07-06

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L21/28273 ,  H01L29/42324

摘要： A method is disclosed to form a split-gate flash memory cell having nitride spacers formed on a pad oxide and prior the forming of an inter-poly oxide layer thereover. In this manner, any damage that would normally occur to the inter-poly oxide during the etching of the nitride spacers subsequent to the forming of the inter-poly oxide is avoided. Consequently, the variation in the thickness of the inter-poly oxide due to the unpredictable damage to the underlying spacers is also avoided by reversing the order in which the spacers and the inter-poly oxide are formed, including the forming of the pad oxide first. As a result, variation in the erase speed of the inter-gate flash memory cell is prevented, both for cells fabricated on the same wafer as well as on different wafers on same or different production lines.

摘要翻译： 公开了一种形成具有形成在衬垫氧化物上的氮化物间隔物并且之前形成多晶氧化物层的分裂栅极快闪存储器单元的方法。 以这种方式，避免了在形成多晶硅氧化物之前在氮化物间隔物的蚀刻期间多晶氧化物通常会发生的任何损伤。 因此，通过反转形成间隔物和多晶氧化物的顺序，包括首先形成衬垫氧化物，也可以避免由于对下面的间隔物的不可预测的损伤而导致的多晶氧化物厚度的变化 。 结果，对于在同一晶片上以及相同或不同生产线上的不同晶片上制造的单元，都能够防止栅极间闪存单元的擦除速度的变化。

公开(公告)号：US6165845A

公开(公告)日：2000-12-26

申请号：US298931

申请日：1999-04-26

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method is provided to form a sharp poly tip to improve the speed of a split-gate flash memory. The sharp poly tip is provided in place of the conventional gate bird's beak (GBB) because the latter requires the forming of thick poly-oxide which is more and more difficult in the miniaturized circuits of the ultra scale integrated technology. Furthermore, it is well known that GBB encroaches under the gate edge in a split-gate flash and degrades the programmability of submicron memory cells. The sharp poly tip of the invention is provided by forming a tapered floating gate through a high pressure etch such that the tip of the upper edge of the floating gate under the poly oxide is sharper and more robust, and, therefore, less susceptible to damage during the manufacture of the cell. The invention is also directed to a semiconductor device fabricated by the disclosed method.

摘要翻译： 提供了一种形成尖锐的多晶硅尖端以提高分流栅闪存的速度的方法。 提供尖锐的多头尖端来代替常规的门鸟嘴（GBB），因为后者需要形成在超级集成技术的小型化电路中越来越困难的厚的多晶氧化物。 此外，众所周知，GBB在分割门闪存中的栅极边缘下侵入并降低亚微米存储器单元的可编程性。 通过高压蚀刻形成锥形浮栅，使得多晶氧化物下方的浮栅的上边缘的尖端更清晰，更坚固，因此不易受损害，从而提供本发明的尖锐的多尖端 在电池的制造期间。 本发明还涉及通过所公开的方法制造的半导体器件。

公开(公告)号：US6133096A

公开(公告)日：2000-10-17

申请号：US208917

申请日：1998-12-10

申请人： Hung-Der Su ,  Jong Chen ,  Chrong-Jung Lin ,  Di-Son Kuo

发明人： Hung-Der Su ,  Jong Chen ,  Chrong-Jung Lin ,  Di-Son Kuo

IPC分类号： H01L21/8247 ,  H01L27/105 ,  H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11534

摘要： A process for integrating the fabrication of a flash memory cell, on a first region of a semiconductor substrate, with the fabrication of salicided peripheral devices, on a second region of the semiconductor substrate, has been developed. The flash memory cell features SAC contact structures, located between stacked gate structures, contacting underlying source/drain regions. The stack gate structures are comprised of a polycide control gate shape, on a dielectric layer, overlying a polysilicon floating gate shape. The performance of the peripheral devices are increased via use of metal silicide layers, located on the top surface of a polysilicon gate structure, as well as on the adjacent heavily doped source/drain regions.

摘要翻译： 已经开发了在半导体衬底的第二区域上将闪存单元的制造在半导体衬底的第一区域上与制造水银外围器件进行集成的工艺。 闪存单元具有位于层叠栅极结构之间的SAC接触结构，接触下层的源/漏区。 堆叠栅极结构由覆盖多晶硅浮栅形状的介电层上的多晶硅控制栅极形状构成。 通过使用位于多晶硅栅极结构的顶表面上的金属硅化物层以及相邻的重掺杂源极/漏极区域来增加外围器件的性能。

公开(公告)号：US6093608A

公开(公告)日：2000-07-25

申请号：US298142

申请日：1999-04-23

申请人： Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Chia-Ta Hsieh

发明人： Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Chia-Ta Hsieh

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L21/8247

CPC分类号： H01L29/42324 ,  H01L21/28273

摘要： A split gate P-channel flash memory cell and method of forming a split gate P-channel flash memory cell which avoids of high erasing voltage, reverse tunneling during programming, drain disturb and over erase problems, and permits shrinking the cell dimensions. The control gate has a concave top surface which intersects with the sidewalls to form a sharp edge. The cell is programmed by charging the floating gate with electrons by means of hot electron injection from the channel into the floating gate. The cell is erased by discharging the excess electrons from the floating gate into the control gate using Fowler-Nordheim tunneling. The sharp edge at the intersection of the concave top surface and the sidewalls of the floating gate produces a high electric field between the control gate and the floating gate to accomplish the Fowler-Nordheim tunneling with only moderate voltage differences between the floating gate and control gate. The P-channel flash memory cell has a higher impact ionization rage for creating hot electrons so that the distance between the source and drain junctions and the length of the floating gate can be kept small thereby permitting the dimensions of the flash memory cell to be shrunk.

公开(公告)号：US6087222A

公开(公告)日：2000-07-11

申请号：US35058

申请日：1998-03-05

申请人： Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

发明人： Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L21/336

CPC分类号： H01L27/11556 ,  H01L21/28273

摘要： A method of forming a vertical transistor memory device includes the following steps. Before forming the trenches, FOX regions are formed between the rows. Form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thick floating gate layer of doped polysilicon over the tunnel oxide layer filling the trenches and extending above the trenches. Etch the floating gate layer down below the top of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thick control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes. Form spacers adjacent to the sidewalls of the control gate electrode.

公开(公告)号：US6074915A

公开(公告)日：2000-06-13

申请号：US135044

申请日：1998-08-17

申请人： Jong Chen ,  Chrong Jung Lin ,  Hung-Der Su ,  Di-Son Kuo

发明人： Jong Chen ,  Chrong Jung Lin ,  Hung-Der Su ,  Di-Son Kuo

IPC分类号： H01L21/8247

CPC分类号： H01L27/11526 ,  H01L27/11536

摘要： A combined method of fabricating embedded flash memory cells having salicide and self-aligned contact (SAC) structures is disclosed. The SAC structure of the cell region and the salicide contacts of the peripheral region of the semiconductor device are formed using a single mask. This is accomplished by a judicious sequence of formation and removal of the various layers including the doped first and second polysilicon layers in the memory cell and of the intrinsic polysilicon layer used in the peripheral circuits. Thus, the etching of the self-aligned contact hole of the memory cell is accomplished at the same time the salicided contact hole of the peripheral region is formed. Furthermore, the thin and thick portions of the dual-gate oxide of the two regions are formed as a natural part of the total process without having to resort to photoresist masking of one portion of the gate oxide layer with the attendant contamination problems while removing the portion of the gate oxide in the other region of the substrate.

摘要翻译： 公开了一种制造具有自对准接触（SAC）结构的嵌入式闪存单元的组合方法。 半导体器件的周边区域的单元区域和硅化物触点的SAC结构使用单个掩模形成。 这是通过明确的形成和去除包括存储单元中的掺杂的第一和第二多晶硅层以及在外围电路中使用的本征多晶硅层的各种层的顺序来实现的。 因此，存储单元的自对准接触孔的蚀刻同时实现了周边区域的浸渍接触孔。 此外，两个区域的双栅极氧化物的薄而厚的部分形成为总工艺的天然部分，而不必诉诸于栅极氧化物层的一部分的光致抗蚀剂掩模以及伴随的污染问题，同时去除 栅极氧化物在衬底的另一区域中的部分。

公开(公告)号：US6060360A

公开(公告)日：2000-05-09

申请号：US843183

申请日：1997-04-14

申请人： Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Juang-Ke Yeh

发明人： Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Juang-Ke Yeh

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788 ,  H01L21/8247

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.

摘要翻译： 在掺杂半导体衬底中形成的掺杂硅半导体N阱上制造闪存EEPROM或分离栅极快速EEPROM。 具有给定宽度的通道形成在被隧道氧化物层覆盖的N阱中，以及N +掺杂多晶硅浮栅电极层，其可以被图案化成具有比沟道窄的宽度的分离栅极浮栅 宽度。 在浮栅电极和暴露的隧道氧化物之上形成电极间电介质层。 控制栅电极包括由电极间电介质层上的P +掺杂多晶硅构成的层。 将隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极图案化成沟道上方的栅电极堆叠。 源极区域和漏极区域用P型掺杂剂形成在衬底的表面中，源极区域和漏极区域与栅电极堆叠自对准。

公开(公告)号：US6046086A

公开(公告)日：2000-04-04

申请号：US100691

申请日：1998-06-19

申请人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Di-Son Kuo

发明人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Di-Son Kuo

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  Y10S438/981

摘要： A method is provided for forming a split-gate flash memory cell having reduced size, increased capacitive coupling and improved data retention capability. A split-gate cell is also provided with appropriate gate oxide thicknesses between the substrate and the floating gate and between the floating gate and the control gate along with an extra thin nitride layer formed judiciously over the primary gate oxide layer in order to overcome the problems of low data retention capacity of the floating gate and the reduced capacitive coupling between the floating gate and the source of prior art.

摘要翻译： 提供了一种用于形成具有减小的尺寸，增加的电容耦合和改进的数据保持能力的分离栅极闪存单元的方法。 分离栅极单元还在衬底和浮置栅极之间以及浮置栅极和控制栅极之间提供适当的栅极氧化物厚度，以及在主栅极氧化物层上明智地形成的额外的薄的氮化物层，以克服问题 的浮动栅极的低数据保持容量和现有技术的浮动栅极和源极之间的减小的电容耦合。

公开(公告)号：US6028324A

公开(公告)日：2000-02-22

申请号：US813758

申请日：1997-03-07

申请人： Hung-Der Su ,  Jian-Hsing Lee ,  Di-Son Kuo

发明人： Hung-Der Su ,  Jian-Hsing Lee ,  Di-Son Kuo

IPC分类号： H01L23/544 ,  H01L23/58 ,  H01L27/108

CPC分类号： H01L22/34 ,  H01L2924/0002

摘要： An ensemble of test structures comprising arrays of polysilicon plate MOS capacitors for the measurement of electrical quality of the MOSFET gate insulation is described. The test structures also measure plasma damage to these gate insulators incurred during metal etching and plasma ashing of photoresist. The structures are formed, either on test wafers or in designated areas of wafers containing integrated circuit chips. One of the test structures is designed primarily to minimize plasma damage so that oxide quality, and defect densities may be measured unhampered by interface traps created by plasma exposure. Other structures provide different antenna-to-oxide area ratios, useful for assessing plasma induced oxide damage and breakdown. The current-voltage characteristics of the MOS capacitors are measured by probing the structures on the wafer, thereby providing timely process monitoring capability.

摘要翻译： 描述了包括用于测量MOSFET栅极绝缘的电气质量的多晶硅板MOS电容器阵列的测试结构的集合。 测试结构还测量在金属蚀刻和光致抗蚀剂的等离子体灰化期间引起的这些栅绝缘体的等离子体损伤。 在测试晶片上或在包含集成电路芯片的晶片的指定区域中形成结构。 其中一个测试结构主要设计为最小化等离子体损伤，从而可以通过等离子体暴露产生的界面陷阱来测量氧化物质量和缺陷密度。 其他结构提供不同的天线到氧化物面积比，可用于评估等离子体诱导的氧化物损伤和击穿。 通过探测晶片上的结构来测量MOS电容器的电流 - 电压特性，从而提供及时的过程监控能力。