公开(公告)号：US06246075B1

公开(公告)日：2001-06-12

申请号：US09507883

申请日：2000-02-22

申请人： Hung-Der Su ,  Jian-Hsing Lee ,  Di-Son Kuo

发明人： Hung-Der Su ,  Jian-Hsing Lee ,  Di-Son Kuo

IPC分类号： H01L2358

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ensemble of test structures comprising arrays of polysilicon plate MOS capacitors for the measurement of electrical quality of the MOSFET gate insulation is described. The test structures also measure plasma damage to these gate insulators incurred during metal etching and plasma ashing of photoresist. The structures are formed, either on test wafers or in designated areas of wafers containing integrated circuit chips. One of the test structures is designed primarily to minimize plasma damage so that oxide quality, and defect densities may be measured unhampered by interface traps created by plasma exposure. Other structures provide different antenna-to-oxide area ratios, useful for assessing plasma induced oxide damage and breakdown. The current-voltage characteristics of the MOS capacitors are measured by probing the structures on the wafer, thereby providing timely process monitoring capability.

摘要翻译： 描述了包括用于测量MOSFET栅极绝缘的电气质量的多晶硅板MOS电容器阵列的测试结构的集合。 测试结构还测量在金属蚀刻和光致抗蚀剂的等离子体灰化期间引起的这些栅绝缘体的等离子体损伤。 在测试晶片上或在包含集成电路芯片的晶片的指定区域中形成结构。 其中一个测试结构主要设计为最小化等离子体损伤，从而可以通过等离子体曝光产生的界面陷阱来测量氧化物质量和缺陷密度。 其他结构提供不同的天线到氧化物面积比，可用于评估等离子体诱导的氧化物损伤和击穿。 通过探测晶片上的结构来测量MOS电容器的电流 - 电压特性，从而提供及时的过程监控能力。

公开(公告)号：US6028324A

公开(公告)日：2000-02-22

申请号：US813758

申请日：1997-03-07

申请人： Hung-Der Su ,  Jian-Hsing Lee ,  Di-Son Kuo

发明人： Hung-Der Su ,  Jian-Hsing Lee ,  Di-Son Kuo

IPC分类号： H01L23/544 ,  H01L23/58 ,  H01L27/108

CPC分类号： H01L22/34 ,  H01L2924/0002

摘要： An ensemble of test structures comprising arrays of polysilicon plate MOS capacitors for the measurement of electrical quality of the MOSFET gate insulation is described. The test structures also measure plasma damage to these gate insulators incurred during metal etching and plasma ashing of photoresist. The structures are formed, either on test wafers or in designated areas of wafers containing integrated circuit chips. One of the test structures is designed primarily to minimize plasma damage so that oxide quality, and defect densities may be measured unhampered by interface traps created by plasma exposure. Other structures provide different antenna-to-oxide area ratios, useful for assessing plasma induced oxide damage and breakdown. The current-voltage characteristics of the MOS capacitors are measured by probing the structures on the wafer, thereby providing timely process monitoring capability.

摘要翻译： 描述了包括用于测量MOSFET栅极绝缘的电气质量的多晶硅板MOS电容器阵列的测试结构的集合。 测试结构还测量在金属蚀刻和光致抗蚀剂的等离子体灰化期间引起的这些栅绝缘体的等离子体损伤。 在测试晶片上或在包含集成电路芯片的晶片的指定区域中形成结构。 其中一个测试结构主要设计为最小化等离子体损伤，从而可以通过等离子体暴露产生的界面陷阱来测量氧化物质量和缺陷密度。 其他结构提供不同的天线到氧化物面积比，可用于评估等离子体诱导的氧化物损伤和击穿。 通过探测晶片上的结构来测量MOS电容器的电流 - 电压特性，从而提供及时的过程监控能力。

公开(公告)号：US5933732A

公开(公告)日：1999-08-03

申请号：US851563

申请日：1997-05-07

申请人： Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Jian-Hsing Lee

发明人： Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Jian-Hsing Lee

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0441 ,  G11C16/045 ,  H01L27/115 ,  H01L29/7885

摘要： An FET semiconductor device includes an N-region and a P-region formed in the substrate with the N-region juxtaposed with the P-region with an interface between the N-region and the P-region and with a first channel in the N-region and a second channel in the P-region. An N+ drain region is near the interface on one side of the first channel in the P-region. A P+ drain region is near the interface on one side of the second channel in the N-region. An N+ source region is on the opposite side of the first channel from the interface in the P-region. A P+ source region is on the opposite side of the first channel from the interface in the N-region. A wide gate electrode EEPROM stack bridges the channels in the N-region and the P-region. The stack includes a tunnel oxide layer, a floating gate electrode layer, an interelectrode dielectric layer, and a control gate electrode. An N+ drain region is formed in the surface of the P-region self-aligned with the gate electrode stack. A P+ drain region is formed in the surface of the N-region self-aligned with the gate electrode stack.

摘要翻译： FET半导体器件包括形成在衬底中的N区和P区，其中N区与P区并置，具有N区和P区之​​间的界面，并且N区中的第一通道 - 区域和P区域中的第二个通道。 N +漏极区域位于P区域中第一通道一侧的界面附近。 P +漏极区域位于N区域中第二通道一侧的界面附近。 N +源极区域与第一通道的与P区域中的界面相反。 P +源极区域与N区域中的界面在第一通道的相对侧。 宽栅电极EEPROM堆叠桥接N区和P区中的沟道。 堆叠包括隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极。 在与栅电极堆叠自对准的P区的表面中形成N +漏极区。 在与栅极电极堆叠自对准的N区域的表面中形成P +漏极区域。

公开(公告)号：US06455887B1

公开(公告)日：2002-09-24

申请号：US09320754

申请日：1999-05-27

申请人： Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Jian-Hsing Lee

发明人： Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Jian-Hsing Lee

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  G11C16/0441 ,  G11C16/045 ,  H01L27/115 ,  H01L29/7885

摘要： An FET semiconductor device includes an N-region and a P-region formed in the substrate with the N-region juxtaposed with the P-region with an interface between the N-region and the P-region and with a first channel in the N-region and a second channel in the P-region. An N+ drain region is near the interface on one side of the first channel in the P-region. A P+ drain region is near the interface on one side of the second channel in the N-region. An N+ source region is on the opposite side of the first channel from the interface in the P-region. A P+ source region is on the opposite side of the first channel from the interface in the N-region. A wide gate electrode EEPROM stack bridges the channels in the N-region and the P-region. The stack includes a tunnel oxide layer, a floating gate electrode layer, an interelectrode dielectric layer, and a control gate electrode. An N+ drain region is formed in the surface of the P-region self-aligned with the gate electrode stack. A P+ drain region is formed in the surface of the N-region self-aligned with the gate electrode stack.

摘要翻译： FET半导体器件包括形成在衬底中的N区和P区，其中N区与P区并置，具有N区和P区之​​间的界面，并且N区中的第一通道 - 区域和P区域中的第二个通道。 N +漏极区域位于P区域中第一通道一侧的界面附近。 P +漏极区域位于N区域中第二通道一侧的界面附近。 N +源极区域与第一通道的与P区域中的界面相反。 P +源极区域与N区域中的界面在第一通道的相对侧。 宽栅电极EEPROM堆叠桥接N区和P区中的沟道。 堆叠包括隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极。 在与栅电极堆叠自对准的P区的表面中形成N +漏极区。 在与栅极电极堆叠自对准的N区域的表面中形成P +漏极区域。

公开(公告)号：US06747857B1

公开(公告)日：2004-06-08

申请号：US10062706

申请日：2002-02-01

申请人： Jian-Hsing Lee ,  Hung-Der Su ,  Jiaw-Ren Shih

发明人： Jian-Hsing Lee ,  Hung-Der Su ,  Jiaw-Ren Shih

IPC分类号： H02H900

CPC分类号： H03K17/0822 ,  H01L27/0266 ,  H03K17/6872

摘要： A novel device and process is described for an ESD protection device for complimentary cascaded NMOS output circuit strings. The invention consists of a clamping NMOS with gate connected to the input or output pad through a diode and connected to ground through a resistor. The clamping device drain is connected to the signal gate of the active output NMOS and the clamping device source is connected to ground. An ESD event causes the diode to go into breakdown mode and the conduction current across the resistor places a positive voltage on the clamping device gate turning the clamping device on. This clamps the active NMOS signal gate to ground assuring that the output NMOS remains in an off condition during the ESD event. This prevents any damage due to high current flow through the active, or used output inverter string.

摘要翻译： 对于用于互补级联的NMOS输出电路串的ESD保护器件描述了一种新颖的器件和工艺。 本发明包括一个钳位NMOS，其栅极通过二极管连接到输入或输出焊盘，并通过电阻器连接到地。 钳位装置漏极连接到有源输出NMOS的信号栅极，钳位装置源连接到地。 ESD事件导致二极管进入击穿模式，并且电阻两端的导通电流在夹紧装置门上施加正电压，使夹紧装置打开。 这将有源NMOS信号栅极钳位到地，确保在ESD事件期间输出NMOS保持关断状态。 这可以防止由于高电流流过有源或使用的输出逆变器串造成的任何损坏。

公开(公告)号：US06653709B2

公开(公告)日：2003-11-25

申请号：US10213612

申请日：2002-08-07

申请人： Yi-Hsu Wu ,  Hung-Der Su ,  Jian-Hsing Lee ,  Boon-Khim Liew

发明人： Yi-Hsu Wu ,  Hung-Der Su ,  Jian-Hsing Lee ,  Boon-Khim Liew

IPC分类号： H01L2972

CPC分类号： H01L27/092 ,  H01L21/823814 ,  H01L27/0266

摘要： A new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad. A dummy PMOS transistor has the source and the gate connected to the voltage supply, and the drain connected to the output pad. A driver NMOS cascaded stack comprises first and second NMOS transistors. The first NMOS transistor has the source connected to ground and the gate connected to the input signal. The second NMOS transistor has the gate connected to the voltage supply, the source connected to the first NMOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source. A dummy NMOS cascaded stack comprises third and fourth NMOS transistors. The third NMOS transistor has the gate and the source connected to ground. The fourth NMOS transistor has the gate connected to the voltage supply, the source connected to the third MOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source.

公开(公告)号：US06765772B2

公开(公告)日：2004-07-20

申请号：US09963559

申请日：2001-09-27

申请人： Jian-Hsing Lee ,  Hung-Der Su

发明人： Jian-Hsing Lee ,  Hung-Der Su

IPC分类号： H02H900

CPC分类号： H01L27/0251

摘要： The present invention determines the ESD event by detecting the voltage value of the power source. The numbers N of the diodes 441 have to follow the condition of: N×VT(0.7)>Vcc (core) Therefore, the diodes 441 will not influence normal operation outside of ESD events. When an ESD pulse is generated, the PN junction of the PMOS transistor is turned on, so the voltage value of Vcc is raised. At this time, the voltage value of Vcc (core) is “Vcc−0.7−N1×(0.7)”, N1 represents the numbers of diodes between Vcc (core) and Vcc, which follows the condition of “N1×(0.7)>Vcc—Vcc (core)” to ensure the diodes remain turned on in normal operation.

摘要翻译： 本发明通过检测电源的电压值来确定ESD事件。 二极管441的数量N必须遵循以下条件：因此，二极管441不会影响ESD事件之外的正常工作。 当产生ESD脉冲时，PMOS晶体管的PN结导通，因此Vcc的电压值升高。 此时，Vcc（磁芯）的电压值为“Vcc-0.7-N1x（0.7）”，N1表示Vcc（磁芯）与Vcc之间的二极管数，其为“N1x（0.7）> Vcc -Vcc（核心）“，以确保二极管在正常工作状态下保持接通。

公开(公告)号：US06414532B1

公开(公告)日：2002-07-02

申请号：US09963596

申请日：2001-09-27

申请人： Hung Der Su ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  Mau-Lin Wu

发明人： Hung Der Su ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  Mau-Lin Wu

IPC分类号： H03K508

CPC分类号： H01L27/0266

摘要： An I/O ESD protection circuit is provided utilizing a driver circuit, an ESD protection circuit, a Vcc/Vss protection circuit, and a clamping circuit. The driver circuit and the ESD protection circuit each comprise a NMOS cascode circuit. NMOS transistors and biasing resistive means comprise the Vcc/Vss protection circuit. The clamping circuit is a diode coupled between the I/O pad of the protection circuit and the gate of that NMOS transistor. In an ESD event the diode turns on the NMOS transistor of the Vcc/Vss protection circuit , thus clamping off the first transistor of both NMOS cascode circuits. The clamping inhibits the gate of those first two transistors to be coupled up by an ESD voltage and creates a parasitic bipolar transistor in each cascode circuit. The parasitic bipolar transistors provide a uniform current flow in the buried area of the P-well of both NMOS cascode circuits.

摘要翻译： 使用驱动电路，ESD保护电路，Vcc / Vss保护电路和钳位电路来提供I / O ESD保护电路。 驱动电路和ESD保护电路各自包括NMOS共源共栅电路。 NMOS晶体管和偏置电阻装置包括Vcc / Vss保护电路。 钳位电路是耦合在保护电路的I / O焊盘和该NMOS晶体管的栅极之间的二极管。 在ESD事件中，二极管导通Vcc / Vss保护电路的NMOS晶体管，因此钳位了两个NMOS共源共栅电路的第一个晶体管。 钳位禁止这些前两个晶体管的栅极通过ESD电压耦合，并在每个共源共栅电路中产生寄生双极晶体管。 寄生双极晶体管在两个NMOS共源共栅电路的P阱的掩埋区域中提供均匀的电流。

公开(公告)号：US09362384B2

公开(公告)日：2016-06-07

申请号：US14559542

申请日：2014-12-03

申请人： Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

发明人： Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L29/66681 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

公开(公告)号：US20150079755A1

公开(公告)日：2015-03-19

申请号：US14559542

申请日：2014-12-03

申请人： Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

发明人： Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

IPC分类号： H01L29/66

CPC分类号： H01L29/66681 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

摘要翻译： 本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS器件包括：第一导电类型衬底，第二导电型高压阱，栅极，第一导电类型体区域，第二导电类型源极，第二导电类型漏极，第一导电型体电极和 第一导电型浮动区域。 浮动区域形成在电气浮动并且与源极和栅极电隔离的体区中，使得减轻静电放电（ESD）效应。