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    Simulation parameter correction technique
    42.
    发明授权
    Simulation parameter correction technique 有权
    模拟参数校正技术

    公开(公告)号：US08713489B2

    公开(公告)日：2014-04-29

    申请号：US13052243

    申请日：2011-03-21

    Applicant: Hiroyuki Higuchi ,  Hidetoshi Matsuoka

    Inventor： Hiroyuki Higuchi ,  Hidetoshi Matsuoka

    IPC: G06F17/50 ,  G01R27/28 ,  G01R31/10 ,  G01R31/14

    CPC classification number: G06F17/5009 ,  G01R27/28 ,  G01R31/10 ,  G01R31/14 ,  G06F17/5045 ,  G06F17/5081 ,  G06F2217/02 ,  G06F2217/10 ,  G06F2217/12 ,  G06F2217/14

    Abstract: A parameter correction method includes: obtaining, from a variability-aware simulation, a simulation result value of a predetermined product performance for a reference candidate value set concerning statistics of predetermined product characteristics; calculating a likelihood by substituting the reference candidate value set, the obtained simulation result value, statistics of measurement values of the predetermined product characteristics and a measurement value of the predetermined product performance into a likelihood function that is defined from a probability density function for the statistics of the predetermined product characteristics and a probability density function for the predetermined product performance, and is a function to calculate a combined likelihood of the statistics of the predetermined product characteristics and the predetermined product performance; and searching for a reference candidate value set in case where the calculated likelihood becomes maximum, by carrying out the obtaining and the calculating plural times while changing the reference candidate value set.

    Abstract translation: 一种参数校正方法，包括：从可变性感知模拟获得关于预定产品特性的统计的参考候选值集合的预定产品性能的仿真结果值; 通过将所述参考候选值集合，所获得的模拟结果值，所述预定乘积特性的测量值和所述预定乘积性能的测量值的统计量代入从用于统计的概率密度函数定义的似然函数中来计算似然度 的预定产品特性的概率密度函数和用于预定产品性能的概率密度函数，并且是计算预定产品特性和预定产品性能的统计的组合可能性的函数; 以及通过在改变所述参考候选值集合的同时执行所述获得和多次计算来搜索所计算的似然性变为最大的情况下设置的参考候选值。

    Semiconductor memory and manufacturing method
    43.
    发明申请
    Semiconductor memory and manufacturing method 审中-公开
    半导体存储器及制造方法

    公开(公告)号：US20120155196A1

    公开(公告)日：2012-06-21

    申请号：US13137672

    申请日：2011-09-01

    Applicant: Yoshinori Tomita ,  Hidetoshi Matsuoka ,  Hiroyuki Higuchi

    Inventor： Yoshinori Tomita ,  Hidetoshi Matsuoka ,  Hiroyuki Higuchi

    IPC: G11C7/00 ,  H01L21/66

    CPC classification number: G11C29/808 ,  G11C29/846 ,  G11C29/848 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor memory includes a memory cell array that includes data cells of x bits and redundant cells of y bits for each word; a position-data storage unit that stores, for each word, defective-cell position data of defective cells of the data cells and the redundant cells; and a read circuit that reads data from cells of x bits based on the defective-cell position data stored in the position-data storage unit for a specified word of which address is specified as read address, the cells of x bits being formed by the data cells of x bits and the redundant cells of y bits of the specified word other than the defective cells.

    Abstract translation: 半导体存储器包括存储单元阵列，其包括x位的数据单元和用于每个字的y位的冗余单元; 位置数据存储单元，针对每个单词存储数据单元和冗余单元的缺陷单元的缺陷单元位置数据; 以及读取电路，其基于存储在所述位置数据存储单元中的针对指定为读取地址的指定字的所述位置数据存储单元中的缺陷单元位置数据从x位的单元读取数据，所述x位的单元由 x位的数据单元和除了有缺陷单元之外的指定字的y位的冗余单元。

    COMPUTER READABLE NON-TRANSITORY MEDIUM STORING DESIGN AIDING PROGRAM, DESIGN AIDING APPARATUS, AND DESIGN AIDING METHOD
    44.
    发明申请
    COMPUTER READABLE NON-TRANSITORY MEDIUM STORING DESIGN AIDING PROGRAM, DESIGN AIDING APPARATUS, AND DESIGN AIDING METHOD 有权
    计算机可读非中继存储设计辅助程序，设计辅助设备和设计辅助方法

    公开(公告)号：US20120117526A1

    公开(公告)日：2012-05-10

    申请号：US13210945

    申请日：2011-08-16

    Applicant: Hiroyuki Higuchi ,  Hidetoshi Matsuoka

    Inventor： Hiroyuki Higuchi ,  Hidetoshi Matsuoka

    IPC: G06F17/50

    CPC classification number: G06F17/5036 ,  G06F17/504

    Abstract: A computer readable non-transitory medium storing a design aiding program causes a computer to execute a process of determining worst-case corner candidates for each of a plurality of condition sets. The design aiding program causes the computer to execute a process of mapping the worst-case corner candidates that are within an allowable range. The design aiding program causes a computer to execute a process of determining the worst-case corner candidates that minimize the number of the worst-case corner candidates mapped to the condition sets by handling the worst-case corner candidates thus mapped as a single worst-case corner candidate to be worst-case corners.

    Abstract translation: 存储设计辅助程序的计算机可读非暂时介质使得计算机执行确定多个条件集合中的每一个的最差情况角候选的处理。 设计辅助程序使得计算机执行映射在允许范围内的最差情况角候选的过程。 设计辅助程序使得计算机执行一个确定最坏情况下角落候选的过程，该候选的最差情况下，通过处理最坏情况的角落候选，将最坏情况下的角点候选映射到条件集， 情况角候选人是最坏的角落。

    Clock gating analyzing apparatus, clock gating analyzing method, and computer product
    45.
    发明授权
    Clock gating analyzing apparatus, clock gating analyzing method, and computer product 有权
    时钟选通分析装置，时钟选通分析方法和计算机产品

    公开(公告)号：US08069026B2

    公开(公告)日：2011-11-29

    申请号：US12002349

    申请日：2007-12-17

    Applicant: Hiroyuki Higuchi

    Inventor： Hiroyuki Higuchi

    IPC: G06F17/50

    CPC classification number: G06F17/5031

    Abstract: Clock gating analysis of a target circuit having a plurality of clock gates, involves the calculation of a clock gate function for each of the clock gates. The clock gate functions indicate an activation state of the clock gates and a combination of output values from sequential circuit elements in the target circuit are substituted into each of the clock gate functions to obtained clock gate function values. Combinations of the clock gate function values form individual clock gating states. Each clock gating state indicates an activation state of each of the local clocks, collectively. A table indicating correlations between the combinations of output values and the clock gating states is generated and from the conversion table, a group that includes all of the clock gating states possible is output.

    Abstract translation: 具有多个时钟门的目标电路的时钟选通分析涉及每个时钟门的时钟门功能的计算。 时钟门功能指示时钟门的激活状态，并且将来自目标电路中的时序电路元件的输出值的组合代入每个时钟门功能以获得时钟门功能值。 时钟门功能值的组合形成单独的时钟选通状态。 每个时钟门控状态统一表示每个本地时钟的激活状态。 产生指示输出值和时钟选通状态的组合之间的相关性的表，并且从转换表可以输出包括所有可能的时钟选通状态的组。

    LSI analysis method, LSI analysis apparatus, and computer product
    46.
    发明授权
    LSI analysis method, LSI analysis apparatus, and computer product 有权
    LSI分析方法，LSI分析装置和计算机产品

    公开(公告)号：US07552411B2

    公开(公告)日：2009-06-23

    申请号：US11655189

    申请日：2007-01-19

    Applicant: Hiroyuki Higuchi

    Inventor： Hiroyuki Higuchi

    IPC: G06F17/50 ,  G06F9/45

    CPC classification number: G06F17/5036 ,  G06F17/5045

    Abstract: In an LSI analysis apparatus, a logic element pair extracting unit extracts an unselected logic element pair when an input unit receives circuit description input. A searching unit searches for an input pattern causing the extracted pair to perform concurrent transition. When an input pattern causing concurrent transition is found, the searching unit determines the extracted pair to be a pair capable of concurrent transition (concurrent transition pair), and holds the input pattern causing concurrent transition. When an input pattern causing concurrent transition is not found, the searching unit determines the extracted pair to be a non-concurrent transition pair. An input pattern operation ratio calculating unit calculates an input pattern operation ratio for each input pattern causing concurrent transition. A detecting unit detects an input pattern yielding the highest input pattern operation ratio. An output unit puts out the detected input pattern, non-concurrent transition pairs, etc.

    Abstract translation: 在LSI分析装置中，当输入单元接收到电路描述输入时，逻辑单元对提取单元提取未选择的逻辑单元对。 搜索单元搜索导致提取的对执行并发转换的输入模式。 当发现引起并发转换的输入模式时，搜索单元将所提取的对确定为能够并发转换的对（并发转移对），并且保持引起并发转换的输入模式。 当没有找到引起并发转换的输入模式时，搜索单元将提取的对决定为非并发转换对。 输入图案运算比计算单元计算引起并发转换的每个输入图形的输入图案运算率。 检测单元检测产生最高输入图案操作比的输入图案。 输出单元输出检测到的输入模式，非并发转换对等

    Method and apparatus for creating simplified false-path description on false path, and computer product
    47.
    发明授权
    Method and apparatus for creating simplified false-path description on false path, and computer product 有权
    用于在虚假路径上创建简化假路径描述的方法和装置，以及计算机产品

    公开(公告)号：US07441217B2

    公开(公告)日：2008-10-21

    申请号：US11521148

    申请日：2006-09-14

    Applicant: Hiroyuki Higuchi

    Inventor： Hiroyuki Higuchi

    IPC: G06F17/50

    CPC classification number: G06F17/5031 ,  G01R31/31725 ,  G01R31/318357 ,  G06F2217/84

    Abstract: An apparatus for creating a simplified false-path description on a false path among paths in a target circuit extracts, from descriptions on the paths, a target path description on a target path. The apparatus judges whether the target path is a false path based on the target path description. The apparatus identifies, when it is judged that the target path is a false path, a sufficient set of elements from elements included in the target path. The settings for causing every element in the sufficient set to transmit a signal conflict. The apparatus creates the simplified false-path description on the false path by deleting, from the target path description, a description on elements that are not included in the sufficient set.

    Abstract translation: 用于在目标电路中的路径中的伪路径上创建简化的假路径描述的装置从路径的描述中提取目标路径上的目标路径描述。 该装置基于目标路径描述来判断目标路径是否为假路径。 当判断目标路径是假路径时，该装置识别包括在目标路径中的元素的足够的一组元素。 用于使足够的集合中的每个元素发送信号冲突的设置。 该装置通过从目标路径描述中删除不包括在足够集合中的元素的描述来在虚假路径上创建简化的假路径描述。

    False path detection program
    48.
    发明授权
    False path detection program 有权
    虚路径检测程序

    公开(公告)号：US07398424B2

    公开(公告)日：2008-07-08

    申请号：US10827690

    申请日：2004-04-19

    Applicant: Hiroyuki Higuchi

    Inventor： Hiroyuki Higuchi

    IPC: G06F11/00

    CPC classification number: G06F17/5031

    Abstract: A false path detection program whereby passing points of signal lines constituting false paths are directly detected, thereby shortening the processing time necessary for the false path detection and the processing time of tools utilizing false path information. A storing section stores, in a storage device, circuit information about a circuit designed by a designer. A signal value generating section generates an impossible signal value with respect to a signal line in the circuit. A signal propagation inspecting section assigns the signal value generated by the signal value generating section to an input of a gate connected to the signal line with respect to which the signal value has been generated, and examines whether signal is propagated through the other input of the gate only when accompanied by the signal value. If signal is propagated through the other input of the gate, a passing point acquiring section acquires a passing point of the other signal line connected to the other input of the gate. A false path specifying section specifies a false path by the passing point acquired by the passing point acquiring section.

    Abstract translation: 直接检测构成虚假路径的信号线的通过点的错误路径检测程序，从而缩短假路径检测所需的处理时间和利用错误路径信息的工具的处理时间。 存储部在存储装置中存储有关由设计者设计的电路的电路信息。 信号值生成部生成相对于电路中的信号线的不可能信号值。 信号传播检查部将由信号值生成部生成的信号值分配给与信号值生成的信号线连接的栅极的输入，并检查信号是否通过其他输入传播 门只有在伴随着信号值的时候。 如果信号通过门的另一输入传播，则通过点获取部分获取连接到门的另一个输入端的另一个信号线的通过点。 伪路径指定部通过由通过点获取部获取的通过点来指定假路径。

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