公开(公告)号：US07605628B2

公开(公告)日：2009-10-20

申请号：US11745108

申请日：2007-05-07

Applicant: Terence J. Magee ,  Thomas Hughes ,  Hui-Yin Seto

Inventor： Terence J. Magee ,  Thomas Hughes ,  Hui-Yin Seto

IPC: H03H11/26

CPC classification number: H03K5/131 ,  H03K2005/00058 ,  H03K2005/00234

Abstract: A method for glitch-free updates of a standard cell-based programmable delay including the steps of (A) generating an output signal in response to an input signal and a plurality of first control signals and (B) generating the plurality of first control signals in response to the output signal and a plurality of second control signals. The output signal may include a delayed version of the input signal. An amount of delay between the input signal and the output signal may be determined based upon the plurality of first control signals.

Abstract translation: 一种用于无毛刺更新标准单元的可编程延迟的方法，包括以下步骤：（A）响应于输入信号和多个第一控制信号产生输出信号，以及（B）产生多个第一控制信号 响应于输出信号和多个第二控制信号。 输出信号可以包括输入信号的延迟版本。 可以基于多个第一控制信号来确定输入信号和输出信号之间的延迟量。

公开(公告)号：US07525356B2

公开(公告)日：2009-04-28

申请号：US11531829

申请日：2006-09-14

Applicant: Keven Hui ,  Ting Fang ,  Hui Yin Seto

Inventor： Keven Hui ,  Ting Fang ,  Hui Yin Seto

IPC: H03L7/00

CPC classification number: H03H11/26

Abstract: A system, apparatus and method for delaying a signal, such as a high-speed signal are disclosed. A multi-stage delay cell is described in which the amount of delay applied to a signal depends on which stages are activated within the cell. In various embodiments of the invention, noise caused by transitions between various delay times within the cell is reduced by efficiently managing voltage states on each of the stages.

Abstract translation: 公开了一种用于延迟诸如高速信号的信号的系统，装置和方法。 描述了多级延迟单元，其中施加到信号的延迟量取决于在单元内激活的阶段。 在本发明的各种实施例中，通过有效地管理每个级上的电压状态来减小由单元内的各种延迟时间之间的转变引起的噪声。

公开(公告)号：US07510431B2

公开(公告)日：2009-03-31

申请号：US11974572

申请日：2007-10-15

Applicant: Zi-Qiang Zhu ,  Xing-Hai Xiang ,  Kai Chen ,  Xiao-Hui Yin

Inventor： Zi-Qiang Zhu ,  Xing-Hai Xiang ,  Kai Chen ,  Xiao-Hui Yin

IPC: H01R13/60

CPC classification number: H01R12/7029 ,  H01R13/508 ,  H01R13/6595

Abstract: An electrical connector (100) includes an insulative housing (10), a number of contacts (20) retained in the insulative housing, a metal shell (30) shielding the insulative housing, and a pair of board locks (40). The insulative housing has a body portion (11) and a mating portion (12). The body portion defines a pair of receiving spaces (14) extending therethrough. Each board lock has a first plate (41) with a hollow cylinder (44) and a hook section (42) extending out of the insulative housing. The metal shell defines a pair of through holes (33) corresponding to the hollow cylinders respectively. The metal shell and the insulative housing sandwich the first plates of the board locks therebetween.

Abstract translation: 电连接器（100）包括绝缘壳体（10），保持在绝缘壳体中的多个触点（20），屏蔽绝缘壳体的金属壳（30）和一对板锁（40）。 绝缘壳体具有主体部分（11）和配合部分（12）。 主体部分限定了一对延伸穿过其中的接收空间（14）。 每个板锁具有带有中空圆柱体（44）的第一板（41）和延伸出绝缘壳体的钩部分（42）。 金属壳体分别对应于中空圆柱体的一对通孔（33）。 金属外壳和绝缘壳体将板的第一板夹在其间。

公开(公告)号：US07443741B2

公开(公告)日：2008-10-28

申请号：US11176041

申请日：2005-07-07

Applicant: Derrick Sai-Tang Butt ,  Hui-Yin Seto

Inventor： Derrick Sai-Tang Butt ,  Hui-Yin Seto

IPC: G11C7/00

CPC classification number: G11C7/1006 ,  G11C7/1066 ,  G11C7/22 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2207/2254

Abstract: A method for calibrating a data valid window including the steps of: (A) setting a base delay of one or more datapaths to a predetermined value, (B) determining an optimum offset delay value for each of the one or more datapaths based upon actual memory accesses and (C) delaying a read data strobe signal based upon the base delay and the optimum offset delay value for each of the one or more datapaths.

Abstract translation: 一种用于校准数据有效窗口的方法，包括以下步骤：（A）将一个或多个数据路径的基本延迟设置为预定值，（B）基于实际值确定所述一个或多个数据通路中的每一个的最佳偏移延迟值 存储器访问和（C）基于所述一个或多个数据路径中的每一个的基本延迟和最佳偏移延迟值来延迟读取数据选通信号。

公开(公告)号：US20080068060A1

公开(公告)日：2008-03-20

申请号：US11531829

申请日：2006-09-14

Applicant: Keven Hui ,  Ting Fang ,  Hui Yin Seto

Inventor： Keven Hui ,  Ting Fang ,  Hui Yin Seto

IPC: H03H11/26

CPC classification number: H03H11/26

Abstract: A system, apparatus and method for delaying a signal, such as a high-speed signal are disclosed. A multi-stage delay cell is described in which the amount of delay applied to a signal depends on which stages are activated within the cell. In various embodiments of the invention, noise caused by transitions between various delay times within the cell is reduced by efficiently managing voltage states on each of the stages.

Abstract translation: 公开了一种用于延迟诸如高速信号的信号的系统，装置和方法。 描述了多级延迟单元，其中施加到信号的延迟量取决于在单元内激活的阶段。 在本发明的各种实施例中，通过有效地管理每个级上的电压状态来减小由单元内的各种延迟时间之间的转变引起的噪声。

公开(公告)号：US20060291302A1

公开(公告)日：2006-12-28

申请号：US11166292

申请日：2005-06-24

Applicant: Hui-Yin Seto ,  Derrick Butt

Inventor： Hui-Yin Seto ,  Derrick Butt

IPC: G11C7/00

CPC classification number: G11C7/1066 ,  G11C7/1051 ,  G11C7/22

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may include a plurality of first multiplexers and one or more second multiplexers configured to generate a first intermediate enable signal in response to (i) an input enable signal, (ii) a first clock signal operating at a first data rate and (iii) a plurality of first select signals. The plurality of first multiplexers each present an output to each of the one or more second multiplexers. The second circuit may be configured to generate a second intermediate enable signal in response to (i) the first intermediate enable signal, (ii) a second clock signal operating at a second data rate and (iii) a second select signal. The third circuit may be configured to generate a third intermediate enable signal in response to (i) the second intermediate enable signal, (ii) a control input signal and (iii) a third select signal. The third intermediate enable signal may be configured to control a read operation of a memory.

Abstract translation: 一种包括第一电路，第二电路和第三电路的装置。 第一电路可以包括多个第一多路复用器和一个或多个第二多路复用器，其被配置为响应于（i）输入使能信号，（ii）以第一数据速率操作的第一时钟信号和（ iii）多个第一选择信号。 多个第一多路复用器各自向一个或多个第二多路复用器中的每一个提供输出。 第二电路可以被配置为响应于（i）第一中间使能信号，（ii）以第二数据速率操作的第二时钟信号和（iii）第二选择信号来产生第二中间使能信号。 第三电路可以被配置为响应于（i）第二中间使能信号，（ii）控制输入信号和（iii）第三选择信号而产生第三中间​​使能信号。 第三中间使能信号可以被配置为控制存储器的读取操作。

公开(公告)号：US5686631A

公开(公告)日：1997-11-11

申请号：US678211

申请日：1996-07-11

Applicant: Hui-Yin Li ,  Andrea Jane Robinson

Inventor： Hui-Yin Li ,  Andrea Jane Robinson

IPC: C07D20060101 ,  C07D311/56 ,  C07D311/02

CPC classification number: C07D311/56

Abstract: The present invention provides a novel process for making compounds of formula 2a or 2b or pharmaceutically acceptable salts thereof, ##STR1## wherein R1 is selected from the group consisting of phenyl and phenyl substituted with at least one group selected from NO.sub.2 and halogen; R.sub.2 is H; R.sub.3 is selected from the group consisting of C.sub.1-4 alkyl, phenyl, and benzyl; and, R.sub.4 is selected from the group consisting of H and halogen; which comprises the steps of: a) oxidizing a racemate of formula 2 or a salt thereof to form a dehydro-compound of formula 3, ##STR2## wherein R.sub.5 is selected from the group consisting of H, CH.sub.3, benzyl, C.sub.2-8 acyl Na, Li and K; and, b) asymmetrically hydrogenating a compound of formula 3 in the presence of a chiral phosphine catalyst to form a compound of formula 2a or 2b.

Abstract translation: 本发明提供制备式2a或2b化合物或其药学上可接受的盐的新方法，其中R 1选自苯基和至少被取代的苯基 一个选自NO2和卤素的基团; R2为H; R 3选自C 1-4烷基，苯基和苄基; 并且R 4选自H和卤素; 其包括以下步骤：a）氧化式2的外消旋物或其盐以形成式3的脱氢化合物，其中H，CH 3，苄基，C 2-8酰基Na，Li和K ; 和b）在手性膦催化剂的存在下不对称地氢化式3的化合物以形成式2a或2b的化合物。

公开(公告)号：USD1018632S1

公开(公告)日：2024-03-19

申请号：US29845378

申请日：2022-07-07

Applicant: Hui Yin

Designer： Hui Yin

Abstract: FIG. 1 is a front perspective view of a dash cam showing my new design;
FIG. 2 is a rear perspective view thereof;
FIG. 3 is a front view thereof;
FIG. 4 is a rear view thereof;
FIG. 5 is a left side view thereof;
FIG. 6 is a right side view thereof;
FIG. 7 is a top plan view thereof; and,
FIG. 8 is a bottom plan thereof.
The broken lines shown in the drawings represent portions of the dash cam that form no part of the claimed design.

公开(公告)号：USD1018631S1

公开(公告)日：2024-03-19

申请号：US29845376

申请日：2022-07-07

Applicant: Hui Yin

Designer： Hui Yin

Abstract: FIG. 1 is a front perspective view of a dash cam showing my new design;
FIG. 2 is a rear perspective view thereof;
FIG. 3 is a front view thereof;
FIG. 4 is a rear view thereof;
FIG. 5 is a left side view thereof;
FIG. 6 is a right side view thereof;
FIG. 7 is a top plan view thereof; and,
FIG. 8 is a bottom plan thereof.
The broken lines shown in the drawings represent portions of the dash cam that form no part of the claimed design.

公开(公告)号：US08765734B2

公开(公告)日：2014-07-01

申请号：US13043986

申请日：2011-03-09

Applicant: Taisheng Huang ,  Chu-Biao Xue ,  Hui-Yin Li ,  Qun Li

Inventor： Taisheng Huang ,  Chu-Biao Xue ,  Hui-Yin Li ,  Qun Li

IPC: C07D487/04 ,  A61K31/519 ,  C07D471/04 ,  C07D401/14 ,  C07D405/14 ,  A61P35/00 ,  A61P29/00 ,  A61P19/02 ,  C07D519/00

CPC classification number: A61K31/4545 ,  A61K9/0014 ,  A61K9/0019 ,  A61K9/0024 ,  A61K9/0048 ,  A61K31/519 ,  A61P1/00 ,  A61P11/00 ,  A61P11/06 ,  A61P27/02 ,  A61P35/00 ,  C07B2200/13 ,  C07D401/14 ,  C07D405/14 ,  C07D471/04 ,  C07D487/04 ,  C07D519/00

Abstract: The present invention provides piperidin-4-yl azetidine derivatives, as well as their compositions and methods of use, that modulate the activity of Janus kinase 1 (JAK1) and are useful in the treatment of diseases related to the activity of JAK1 including, for example, inflammatory disorders, autoimmune disorders, cancer, and other diseases.

Abstract translation: 本发明提供哌啶-4-基氮杂环丁烷衍生物及其组合物和使用方法，其调节Janus激酶1（JAK1）的活性，并且可用于治疗与JAK1的活性相关的疾病，包括对于 例如炎症性疾病，自身免疫性疾病，癌症和其它疾病。