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    Memory interface architecture for maximizing access timing margin
    2.
    发明授权
    Memory interface architecture for maximizing access timing margin 失效
    存储器接口架构，用于最大化访问时序裕量

    公开(公告)号：US08230143B2

    公开(公告)日：2012-07-24

    申请号：US11097903

    申请日：2005-04-01

    Applicant: Hui-Yin Seto ,  Cheng-Gang Kong

    Inventor： Hui-Yin Seto ,  Cheng-Gang Kong

    IPC: G06F13/10

    CPC classification number: G06F13/1689

    Abstract: An apparatus comprising a control circuit, a buffer circuit and a memory. The control circuit may be configured to present a plurality of pairs of signals in response to (i) one or more input signals operating at a first data rate and (ii) an input clock signal operating at a second data rate. The second signal in each of the pairs comprises a clock signal operating at the second data rate. The buffer circuit may be configured to generate a buffered signal in response to each of the pairs of signals. Each of the buffered signals operates at the second data rate. The memory may be configured to read and write data at the second data rate in response to the buffered signals.

    Abstract translation: 一种包括控制电路，缓冲电路和存储器的装置。 控制电路可以被配置为响应于（i）以第一数据速率操作的一个或多个输入信号和（ii）以第二数据速率操作的输入时钟信号，呈现多对信号对。 每对中的第二信号包括以第二数据速率操作的时钟信号。 缓冲电路可以被配置为响应于每对信号产生缓冲信号。 每个缓冲信号以第二数据速率工作。 存储器可以被配置为响应于缓冲的信号以第二数据速率读取和写入数据。

    SYSTEM FOR GLITCH-FREE DELAY UPDATES OF A STANDARD CELL-BASED PROGRAMMABLE DELAY
    3.
    发明申请
    SYSTEM FOR GLITCH-FREE DELAY UPDATES OF A STANDARD CELL-BASED PROGRAMMABLE DELAY 失效
    基于标准电池可编程延时的无刷延时更新系统

    公开(公告)号：US20080278210A1

    公开(公告)日：2008-11-13

    申请号：US11745108

    申请日：2007-05-07

    Applicant: Terence J. Magee ,  Thomas Hughes ,  Hui-Yin Seto

    Inventor： Terence J. Magee ,  Thomas Hughes ,  Hui-Yin Seto

    IPC: H03K5/13 ,  H03H11/26

    CPC classification number: H03K5/131 ,  H03K2005/00058 ,  H03K2005/00234

    Abstract: A method for glitch-free updates of a standard cell-based programmable delay including the steps of (A) generating an output signal in response to an input signal and a plurality of first control signals and (B) generating the plurality of first control signals in response to the output signal and a plurality of second control signals. The output signal may include a delayed version of the input signal. An amount of delay between the input signal and the output signal may be determined based upon the plurality of first control signals.

    Abstract translation: 一种用于无毛刺更新基于标准单元的可编程延迟的方法，包括以下步骤：（A）响应于输入信号和多个第一控制信号产生输出信号，以及（B）产生多个第一控制信号 响应于输出信号和多个第二控制信号。 输出信号可以包括输入信号的延迟版本。 可以基于多个第一控制信号来确定输入信号和输出信号之间的延迟量。

    Method and computer program for generating grounded shielding wires for signal wiring
    5.
    发明授权
    Method and computer program for generating grounded shielding wires for signal wiring 失效
    用于生成信号线接地屏蔽线的方法和计算机程序

    公开(公告)号：US08516425B2

    公开(公告)日：2013-08-20

    申请号：US13544632

    申请日：2012-07-09

    Applicant: Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykih ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

    Inventor： Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykih ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

    IPC: G06F17/50

    CPC classification number: G06F17/505 ,  G06F2217/84

    Abstract: A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.

    Abstract translation: 提供了一种减少信号偏移的系统和方法。 该方法包括接收具有组件之间的组件和连接的网表。 每个连接具有至少一个信号线。 识别多个网络组，每个网络组包括至少一些连接并且期望等效路由。 对于每个网络组，所述方法包括系统地路由用于连接的组件之间的连接路径，每个连接路径在组件之一的输出和至少一个其他组件的输入之间延伸并且包括至少一个路径片段。 对于网络组的至少一个连接，路由包括在与连接路径的路径片段中的至少一个相邻并且平行的路由信道中路由至少一个接地屏蔽线。

    Signal delay skew reduction system
    6.
    发明授权
    Signal delay skew reduction system 有权
    信号延迟偏差减少系统

    公开(公告)号：US07996804B2

    公开(公告)日：2011-08-09

    申请号：US12015925

    申请日：2008-01-17

    Applicant: Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykih ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

    Inventor： Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykih ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

    IPC: G06F17/50

    CPC classification number: G06F17/505 ,  G06F2217/84

    Abstract: A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.

    Abstract translation: 根据各种实施例，公开了一种用于减小信号延迟偏差的系统。 本公开的一个说明性实施例涉及一种方法。 根据一个说明性实施例，该方法包括接收包括组件之间的组件和连接路径的初始网表。 该方法还包括识别在初始网表中的第一连接路径中的一个或多个偏斜影响特征，其在初始网表中的第二连接路径中缺少相应的偏斜影响特征。 该方法还包括生成偏差校正网表，其中第二连接路径包括与第一连接路径的相应的一个或多个相加的偏斜影响特征。 该方法还包括输出经偏斜校正的网表。

    Programmable data strobe enable architecture for DDR memory applications
    7.
    发明授权
    Programmable data strobe enable architecture for DDR memory applications 有权
    可编程数据选通功能支持DDR存储器应用的架构

    公开(公告)号：US07394707B2

    公开(公告)日：2008-07-01

    申请号：US11166292

    申请日：2005-06-24

    Applicant: Hui-Yin Seto ,  Derrick Sai-Tang Butt

    Inventor： Hui-Yin Seto ,  Derrick Sai-Tang Butt

    IPC: G11C7/00

    CPC classification number: G11C7/1066 ,  G11C7/1051 ,  G11C7/22

    Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may include a plurality of first multiplexers and one or more second multiplexers configured to generate a first intermediate enable signal in response to (i) an input enable signal, (ii) a first clock signal operating at a first data rate and (iii) a plurality of first select signals. The plurality of first multiplexers each present an output to each of the one or more second multiplexers. The second circuit may be configured to generate a second intermediate enable signal in response to (i) the first intermediate enable signal, (ii) a second clock signal operating at a second data rate and (iii) a second select signal. The third circuit may be configured to generate a third intermediate enable signal in response to (i) the second intermediate enable signal, (ii) a control input signal and (iii) a third select signal. The third intermediate enable signal may be configured to control a read operation of a memory.

    Abstract translation: 一种包括第一电路，第二电路和第三电路的装置。 第一电路可以包括多个第一多路复用器和一个或多个第二多路复用器，其被配置为响应于（i）输入使能信号，（ii）以第一数据速率操作的第一时钟信号和（ iii）多个第一选择信号。 多个第一多路复用器各自向一个或多个第二多路复用器中的每一个提供输出。 第二电路可以被配置为响应于（i）第一中间使能信号，（ii）以第二数据速率操作的第二时钟信号和（iii）第二选择信号来产生第二中间使能信号。 第三电路可以被配置为响应于（i）第二中间使能信号，（ii）控制输入信号和（iii）第三选择信号而产生第三中间​​使能信号。 第三中间使能信号可以被配置为控制存储器的读取操作。

    Method and/or apparatus for training DQS strobe gating
    8.
    发明申请
    Method and/or apparatus for training DQS strobe gating 失效
    用于训练DQS选通门控的方法和/或装置

    公开(公告)号：US20070002642A1

    公开(公告)日：2007-01-04

    申请号：US11173529

    申请日：2005-07-01

    Applicant: Derrick Butt ,  Hui-Yin Seto

    Inventor： Derrick Butt ,  Hui-Yin Seto

    IPC: G11C7/00

    CPC classification number: G11C7/1066 ,  G06F13/4059 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4076 ,  G11C2207/2254

    Abstract: A method for calibrating read data strobe gating including the steps of: (A) performing a coarse timing adjustment configured to determine a coarse delay setting that produces invalid data, (B) performing a medium timing adjustment configured to adjust a medium delay setting and the coarse delay setting until valid data is detected, (C) performing a fine timing adjustment configured to adjust the medium delay setting and a fine delay setting until valid data is detected and (D) adding one-half cycle to a gating delay determined by the coarse, the medium and the fine delay settings.

    Abstract translation: 一种用于校准读取数据选通门控的方法，包括以下步骤：（A）执行粗调定时调整，其被配置为确定产生无效数据的粗略延迟设置，（B）执行配置成调整中等延迟设置的中等定时调整， 检测到有效数据之前的粗延迟设置，（C）执行精细定时调整，其被配置为调整介质延迟设置和精细延迟设置，直到检测到有效数据，并且（D）将半个周期添加到由 粗调，中等和精细延迟设置。

    Memory interface architecture for maximizing access timing margin
    9.
    发明申请
    Memory interface architecture for maximizing access timing margin 失效
    存储器接口架构，用于最大化访问时序裕量

    公开(公告)号：US20060224847A1

    公开(公告)日：2006-10-05

    申请号：US11097903

    申请日：2005-04-01

    Applicant: Hui-Yin Seto ,  Cheng-Gang Kong

    Inventor： Hui-Yin Seto ,  Cheng-Gang Kong

    IPC: G06F13/00

    CPC classification number: G06F13/1689

    Abstract: An apparatus comprising a control circuit, a buffer circuit and a memory. The control circuit may be configured to present a plurality of pairs of signals in response to (i) one or more input signals operating at a first data rate and (ii) an input clock signal operating at a second data rate. The second signal in each of the pairs comprises a clock signal operating at the second data rate. The buffer circuit may be configured to generate a buffered signal in response to each of the pairs of signals. Each of the buffered signals operates at the second data rate. The memory may be configured to read and write data at the second data rate in response to the buffered signals.

    Abstract translation: 一种包括控制电路，缓冲电路和存储器的装置。 控制电路可以被配置为响应于（i）以第一数据速率操作的一个或多个输入信号和（ii）以第二数据速率操作的输入时钟信号，呈现多对信号对。 每对中的第二信号包括以第二数据速率操作的时钟信号。 缓冲电路可以被配置为响应于每对信号产生缓冲信号。 每个缓冲信号以第二数据速率工作。 存储器可以被配置为响应于缓冲的信号以第二数据速率读取和写入数据。

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