公开(公告)号：US20110242869A1

公开(公告)日：2011-10-06

申请号：US12840250

申请日：2010-07-20

Applicant: Hyung Dong Lee ,  Duk Su Chun ,  Hyun Seok Kim

Inventor： Hyung Dong Lee ,  Duk Su Chun ,  Hyun Seok Kim

IPC: G11C5/02 ,  G11C8/00

CPC classification number: H01L25/0657 ,  G11C5/02 ,  G11C8/12 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A three-dimensional stacked semiconductor integrated circuit including a plurality of stacked chips. The semiconductor integrated circuit is configured to simultaneously select the plurality of chips in response to an external command and an address, and to activate one of memory banks which are aligned on the same line in a vertical direction, among a plurality of memory banks included in the plurality of chips.

Abstract translation: 一种包括多个堆叠芯片的三维堆叠半导体集成电路。 半导体集成电路被配置为响应于外部命令和地址而同时选择多个芯片，并且在包括在多个存储器组中的多个存储器组中激活在垂直方向上在同一行上对准的存储体之一 多个芯片。

公开(公告)号：US07961537B2

公开(公告)日：2011-06-14

申请号：US12829994

申请日：2010-07-02

Applicant: Hyung-Dong Lee

Inventor： Hyung-Dong Lee

IPC: G11C7/00

CPC classification number: G11C29/02 ,  G11C7/08 ,  G11C29/022 ,  G11C29/023 ,  G11C29/50012 ,  G11C2029/4402

Abstract: A semiconductor integrated circuit includes a sense amplifier for sensing input data and a sense amplifier controller for blocking a signal path between the sense amplifier and a memory cell when a test mode signal is activated.

Abstract translation: 半导体集成电路包括用于感测输入数据的读出放大器和用于在测试模式信号被激活时阻塞读出放大器与存储单元之间的信号路径的读出放大器控制器。

公开(公告)号：US20110074369A1

公开(公告)日：2011-03-31

申请号：US12649193

申请日：2009-12-29

Applicant: Yong Kee KWON ,  Hyung Dong Lee ,  Young Park Kim

Inventor： Yong Kee KWON ,  Hyung Dong Lee ,  Young Park Kim

IPC: G05F1/00 ,  H01L23/58

CPC classification number: G11C11/4074 ,  G11C5/147 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

Abstract: A semiconductor apparatus includes a reference voltage generation unit, a comparison voltage generation unit, and a calibration unit. The reference voltage generation unit is disposed in a reference die and configured to generate a reference voltage. The comparison voltage generation unit is disposed in a die stacked on the reference die and configured to generate a comparison voltage in response to a calibration control signal. The calibration unit is configured to compare a level of the reference voltage with a level of the comparison voltage and generate the calibration control signal.

Abstract translation: 半导体装置包括参考电压产生单元，比较电压产生单元和校准单元。 参考电压产生单元设置在参考管芯中，并被配置为产生参考电压。 比较电压产生单元设置在堆叠在参考管芯上的管芯中，并被配置为响应校准控制信号产生比较电压。 校准单元被配置为将参考电压的电平与比较电压的电平进行比较并产生校准控制信号。

公开(公告)号：US20110068822A1

公开(公告)日：2011-03-24

申请号：US12956416

申请日：2010-11-30

Applicant: Yong Kee KWON ,  Hyung Dong LEE

Inventor： Yong Kee KWON ,  Hyung Dong LEE

IPC: H03K17/16

CPC classification number: G11C7/1048 ,  G11C11/4096 ,  G11C11/4097

Abstract: A data line termination circuit includes a swing-width sensing unit configured to sense a swing width of a voltage of a data line and output a sensed signal, and a variable termination unit configured to adjust a termination resistance value of the data line in response to the sensed signal. The swing-width sensing unit can sense if the swing width is less than or greater than a predetermined swing width, and the swing width of the voltage of the data line can be reduced or increased to maintain the voltage of the data line within a predetermined range.

Abstract translation: 数据线终端电路包括：摆动宽度检测单元，被配置为感测数据线的电压的摆幅并输出感测信号;以及可变终端单元，被配置为响应于所述数据线的终端电阻值 感测信号。 摆幅感测单元可以感测摆动宽度是否小于或大于预定的摆动宽度，并且可以减小或增加数据线的电压的摆动宽度，以将数据线的电压保持在预定的 范围。

公开(公告)号：US20100039093A1

公开(公告)日：2010-02-18

申请号：US12480951

申请日：2009-06-09

Applicant: YONG KEE KWON ,  Hyung Dong Lee

Inventor： YONG KEE KWON ,  Hyung Dong Lee

IPC: H03H1/00

CPC classification number: G11C5/147

Abstract: An internal voltage generating circuit of a semiconductor memory apparatus includes a control signal generating unit configured to enable one of a plurality of control signals in response to a calibration code; and a signal variable voltage distributing unit configured to determine a distribution ratio in response to one enabled control signal of the plurality of control signals and generate an internal voltage by distributing an external voltage at the determined distribution ratio.

Abstract translation: 半导体存储装置的内部电压产生电路包括：控制信号生成单元，被配置为响应于校准码启用多个控制信号中的一个; 以及信号可变电压分配单元，被配置为响应于所述多个控制信号的一个使能控制信号来确定分配比，并且通过以所确定的分配比分配外部电压来产生内部电压。

公开(公告)号：US20090256585A1

公开(公告)日：2009-10-15

申请号：US12403549

申请日：2009-03-13

Applicant: Yong Kee KWON ,  Hyung Dong LEE

Inventor： Yong Kee KWON ,  Hyung Dong LEE

IPC: H03K17/16

CPC classification number: G11C7/1048 ,  G11C11/4096 ,  G11C11/4097

Abstract: A data line termination circuit includes a swing-width sensing unit configured to sense a swing width of a voltage of a data line and output a sensed signal, and a variable termination unit configured to adjust a termination resistance value of the data line in response to the sensed signal. The swing-width sensing unit can sense if the swing width is less than or greater than a predetermined swing width, and the swing width of the voltage of the data line can be reduced or increased to maintain the voltage of the data line within a predetermined range.

Abstract translation: 数据线终端电路包括：摆动宽度检测单元，被配置为感测数据线的电压的摆幅并输出感测信号;以及可变终端单元，被配置为响应于所述数据线的终端电阻值 感测信号。 摆幅感测单元可以感测摆动宽度是否小于或大于预定的摆动宽度，并且可以减小或增加数据线的电压的摆动宽度，以将数据线的电压保持在预定的 范围。

公开(公告)号：US20090115505A1

公开(公告)日：2009-05-07

申请号：US12136454

申请日：2008-06-10

Applicant: Hyung-Dong LEE ,  Jun-Ho LEE ,  Dong-Hwee KIM ,  Hwa-Yong YANG

Inventor： Hyung-Dong LEE ,  Jun-Ho LEE ,  Dong-Hwee KIM ,  Hwa-Yong YANG

IPC: G05F1/46

CPC classification number: H03H1/00 ,  H01L23/5223 ,  H01L2924/0002 ,  H03H2001/0064 ,  H01L2924/00

Abstract: Semiconductor device with a controllable decoupling capacitor includes a decoupling capacitor connected between a power voltage terminal and a ground terminal and a switching unit configured to enable/disable the decoupling capacitor in response to a control signal. According to another aspect, a semiconductor device with a controllable decoupling capacitor includes multiple circuits, decoupling capacitors being connected in parallel to each of the circuits and switching units being configured to enable/disable the decoupling capacitors in response to control signals.

Abstract translation: 具有可控去耦电容器的半导体器件包括连接在电源电压端子和接地端子之间的去耦电容器以及被配置为响应于控制信号使能/禁用去耦电容器的开关单元。 根据另一方面，具有可控解耦电容器的半导体器件包括多个电路，去耦电容器并联连接到每个电路，并且开关单元被配置为响应于控制信号启用/禁用去耦电容器。

公开(公告)号：US20070258293A1

公开(公告)日：2007-11-08

申请号：US11647478

申请日：2006-12-29

Applicant: Hyung Dong Lee

Inventor： Hyung Dong Lee

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/108 ,  G11C2207/2254

Abstract: A plurality of first drivers outputs a plurality of data based on first control signals. A second driving unit generates a second control signal synchronized with data output cycles of the first drivers using the first control signals. An amplitude correcting unit corrects an amplitude of the second control signal using at least the first control signals.

Abstract translation: 多个第一驱动器基于第一控制信号输出多个数据。 第二驱动单元使用第一控制信号产生与第一驱动器的数据输出周期同步的第二控制信号。 振幅校正单元至少使用第一控制信号校正第二控制信号的振幅。

公开(公告)号：US06985401B2

公开(公告)日：2006-01-10

申请号：US10857618

申请日：2004-06-01

Applicant: Eun Jung Jang ,  Hyung Dong Lee

Inventor： Eun Jung Jang ,  Hyung Dong Lee

IPC: G11C8/00

CPC classification number: G11C11/4076 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  H03L7/0814

Abstract: A memory device minimizes the skew between an external clock and a DQS (or DQ) after the locking state by regulating a delay ratio of a replica delay model to compensate errors of process, temperature or voltage change. The memory device comprises: an input clock buffer for buffering an externally inputted external clock to generate an internal clock; a DLL for delaying the internal clock to synchronize a phase of the external clock with that of a DQS; an output clock buffer for buffering an output clock outputted from the DLL; and an output control unit for generating the DQS using a clock outputted from the output clock buffer. Here, the DLL comprises a replica delay model for modeling delay factors of the input clock buffer and other delay factors until the output clock outputted from the delay line is outputted to the outside of a chip, and for regulating a delay ratio in response to a plurality of control signals inputted externally in a test mode.

Abstract translation: 存储器件通过调节复制延迟模型的延迟比来补偿过程，温度或电压变化的错误，从而最大限度地减小锁定状态之后的外部时钟和DQS（或DQ）之间的偏差。 存储器件包括：输入时钟缓冲器，用于缓冲外部输入的外部时钟以产生内部时钟; 用于延迟内部时钟以使外部时钟的相位与DQS的相位同步的DLL; 输出时钟缓冲器，用于缓冲从DLL输出的输出时钟; 以及输出控制单元，用于使用从输出时钟缓冲器输出的时钟产生DQS。 这里，DLL包括用于建模输入时钟缓冲器的延迟因子和其他延迟因子的复制延迟模型，直到从延迟线输出的输出时钟被输出到芯片的外部，并且用于响应于 在测试模式下从外部输入的多个控制信号。

公开(公告)号：US06657907B2

公开(公告)日：2003-12-02

申请号：US10144843

申请日：2002-05-15

Applicant: Hyung Dong Lee

Inventor： Hyung Dong Lee

IPC: G11C700

CPC classification number: G11C29/808

Abstract: A column repair circuit of a semiconductor memory is disclosed, in which a column repair efficiency is increased in a row flexible redundancy structure. A repair circuit for a memory divided into arrays and arranged by row lines and column lines crossing each other, the circuit includes a plurality of column fuse boxes for outputting a redundant column enable signal for repairing a defective line, and an array address inverter corresponding to one of the column fuse boxes for inverting a self-pair signal input thereto and a corresponding array address input thereto, the self-pair signal indicating whether a row repair is performed in a corresponding array or in another array, and for selectively outputting the inverted array address according to the self-pair signal.