Flexible circuit support structure and head carrier
    41.
    发明授权
    Flexible circuit support structure and head carrier 失效
    灵活的电路支撑结构和头架

    公开(公告)号:US6078483A

    公开(公告)日:2000-06-20

    申请号:US79109

    申请日:1998-05-14

    申请人: James C. Anderson

    发明人: James C. Anderson

    IPC分类号: G11B5/17 G11B5/49 G11B5/55

    CPC分类号: G11B5/4953

    摘要: A stiffener attached to the magnetic head or heads in a tape drive to support the flexible circuit and provide a flat surface against which the flexible circuit rolls when the head moves up and down. The stiffener is, preferably, fastened to a head carrier that is attached directly to the magnetic head. This head sub-assembly is mounted to the movable carriage that carries the head up and down at the urging of the head positioning actuator.

    摘要翻译: 附着在磁带驱动器中的磁头或磁头的加强件,用于支撑柔性电路,并提供平滑表面,当磁头上下移动时,柔性电路可以滚动。 优选地,加强件紧固到直接附接到磁头的磁头托架上。 该头部组件安装到可移动的托架上,该托架在头部定位致动器的推动下使头部上下移动。

    Pin array set-up device
    42.
    发明授权
    Pin array set-up device 失效
    引脚阵列设置装置

    公开(公告)号:US5834838A

    公开(公告)日:1998-11-10

    申请号:US767446

    申请日:1996-12-16

    申请人: James C. Anderson

    发明人: James C. Anderson

    摘要: An integrated circuit probing method and apparatus therefor. The apparatus includes a main system controller coupled to a network interface, graphic user interface, and equipment interface. A high speed bus connects the main system controller to a group of subsystems. The subsystems includes subsystems such as input cassettes, input frame handing, frame to align, die align, die probing, die bin and die output, output cassettes subsystem, among others. The integrated circuit probing apparatus allows for probing of each individual die through the die probing subsystem, typically a high speed subsystem.

    摘要翻译: 一种集成电路探测方法及其装置。 该装置包括耦合到网络接口,图形用户界面和设备接口的主系统控制器。 高速总线将主系统控制器连接到一组子系统。 子系统包括诸如输入盒,输入框架处理,对准框架,模具对准,模具探测,模具仓和模具输出,输出盒子系统等子系统。 集成电路探测装置允许通过芯片探测子系统(通常是高速子系统)探测每个单独的芯片。

    Die sorter
    43.
    发明授权
    Die sorter 失效
    分模机

    公开(公告)号:US5654204A

    公开(公告)日:1997-08-05

    申请号:US277860

    申请日:1994-07-20

    申请人: James C. Anderson

    发明人: James C. Anderson

    摘要: An integrated circuit probing method and apparatus therefor. The apparatus includes a main system controller coupled to a network interface, graphic user interface, and equipment interface. A high speed bus connects the main system controller to a group of subsystems. The subsystems includes subsystems such as input cassettes, input frame handing, frame to align, die align, die probing, die bin and die output, output cassettes subsystem, among others. The integrated circuit probing apparatus allows for probing of each individual die through the die probing subsystem, typically a high speed subsystem.

    摘要翻译: 一种集成电路探测方法及其装置。 该装置包括耦合到网络接口,图形用户界面和设备接口的主系统控制器。 高速总线将主系统控制器连接到一组子系统。 子系统包括诸如输入盒,输入框架处理,对准框架,模具对准,模具探测,模具仓和模具输出,输出盒子系统等子系统。 集成电路探测装置允许通过芯片探测子系统(通常是高速子系统)探测每个单独的芯片。

    Method of forming tapered plug-filled via in electrical interconnection
    44.
    发明授权
    Method of forming tapered plug-filled via in electrical interconnection 失效
    在电气互连中形成锥形插塞填充通孔的方法

    公开(公告)号:US5567650A

    公开(公告)日:1996-10-22

    申请号:US356421

    申请日:1994-12-15

    IPC分类号: H01L21/768 H01L21/28

    CPC分类号: H01L21/76877 Y10S438/978

    摘要: A process for contouring a via formed in a dielectrics whereby a layer of a refractory metal is formed on the dielectric and in the via. The refractory metal layer is removed until a surface of the refractory metal within the via is below the upper surface of the dielectric. An etching process removes a portion of the dielectric and a tapered shape is formed at the intersection of the via and the upper surface of the dielectric. A second layer of metal is formed over the dielectric, with the second layer of metal extending into the vias and contacting the refractory metal with the tapered shape providing improved step coverage of the second layer of metal at the via.

    摘要翻译: 用于对形成在电介质中的通孔进行轮廓化的方法,由此在电介质和通孔中形成难熔金属层。 去除耐火金属层,直到通孔内的难熔金属的表面低于电介质的上表面。 蚀刻工艺去除电介质的一部分,并且在通孔和电介质的上表面的相交处形成锥形形状。 第二层金属形成在电介质上,第二层金属延伸到通孔中,并使难熔金属与锥形形状接触,从而提供在通孔处的第二金属层的改进的台阶覆盖。

    Probe card system and method
    45.
    发明授权
    Probe card system and method 失效
    探针卡系统和方法

    公开(公告)号:US5506498A

    公开(公告)日:1996-04-09

    申请号:US401327

    申请日:1995-03-09

    IPC分类号: G01R31/28 G01R31/02

    CPC分类号: G01R31/2886

    摘要: A semiconductor wafer probe test interface system (2) and method of operating the system. The wafer probe system includes a plurality of cassettes (302) adapted to hold wafer probe test cards (304). The cassettes are loaded into position for testing of semiconductor wafers with a transport assembly system (6). A memory device (316) on the cassette is used to store data regarding usage of the card such as number of wafer touchdowns. A smart controller (220) has the capability to "talk" to the prober and tester.

    摘要翻译: 一种半导体晶圆探针测试接口系统(2)及其操作方法。 晶片探针系统包括适于保持晶片探针测试卡(304)的多个盒(302)。 将盒装载到用于通过运输组装系统(6)测试半导体晶片的位置。 使用盒上的存储装置(316)来存储关于卡的使用的数据,例如晶片触地次数。 智能控制器(220)具有与探测器和测试仪“通话”的能力。

    Probe card system
    46.
    发明授权
    Probe card system 失效
    探头卡系统

    公开(公告)号:US5254939A

    公开(公告)日:1993-10-19

    申请号:US855763

    申请日:1992-03-20

    IPC分类号: G01R31/28 G01R1/02

    CPC分类号: G01R31/2886

    摘要: A semiconductor wafer probe test interface system (2) and method of operating the system. The wafer probe system includes a plurality of cassettes (302) adapted to hold wafer probe test cards (304). The cassettes are loaded into position for testing of semiconductor wafers with a transport assembly system (6). A memory device (316) on the cassette is used to store data regarding usage of the card such as number of wafer touchdowns. A smart controller (220) has the capability to "talk" to the prober and tester.

    摘要翻译: 一种半导体晶圆探针测试接口系统(2)及其操作方法。 晶片探针系统包括适于保持晶片探针测试卡(304)的多个盒(302)。 将盒装载到用于通过运输组装系统(6)测试半导体晶片的位置。 使用盒上的存储装置(316)来存储关于卡的使用的数据,例如晶片触地次数。 智能控制器(220)具有与探测器和测试仪“通话”的能力。