公开(公告)号：US20080137449A1

公开(公告)日：2008-06-12

申请号：US11636173

申请日：2006-12-08

Applicant: Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

Inventor： Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

IPC: G11C7/00

CPC classification number: G11C11/413

Abstract: A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a source, a drain and a gate coupled to the BL, the Vss and a first data signal, respectively, a second NMOS transistor having a source, a drain and a gate coupled to the BLB, the Vss and a second data signal, respectively, wherein the second data signal is complementary to the first data signal, a first PMOS transistor having a source, a drain and a gate coupled to a high voltage power supply (CVDD) node, the BLB and the BL, respectively, and a second PMOS transistor having a source, a drain and a gate coupled to the CVDD node, the BL and the BLB, respectively.

Abstract translation: 公开了一种写入动态功率控制电路，其包括BL及其互补BLB，耦合到BL和BLB的至少一个存储单元，具有耦合到BL的源极，漏极和栅极的第一NMOS晶体管， Vss和第一数据信号，分别具有耦合到BLB的源极，漏极和栅极的第二NMOS晶体管，Vss和第二数据信号，其中第二数据信号与第一数据信号互补， 第一PMOS晶体管，具有源极，漏极和栅极，分别耦合到高电压电源（CVDD）节点，BLB和BL，以及第二PMOS晶体管，其具有源极，漏极和栅极耦合到 CVDD节点，BL和BLB。

公开(公告)号：US08619488B2

公开(公告)日：2013-12-31

申请号：US13492635

申请日：2012-06-08

Applicant: Yung-Lung Lin ,  Jui-Jen Wu ,  Shine Chung ,  Fu-Lung Hsueh

Inventor： Yung-Lung Lin ,  Jui-Jen Wu ,  Shine Chung ,  Fu-Lung Hsueh

IPC: G11C17/18 ,  G11C17/14 ,  G11C17/16 ,  G11C17/00

CPC classification number: G11C11/5692 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for programming a multi-level electrical fuse system comprises providing a fuse box with an electrical fuse and providing one of at least two fuse writing voltages to the electrical fuse to program the electrical fuse to one of at least two resistance states. The fuse box comprises at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.

Abstract translation: 一种用于编程多电平电熔丝系统的方法包括：提供具有电熔丝的保险丝盒，并向所述电熔丝提供至少两个熔丝写入电压中的一个，以将所述电熔丝编程为至少两个电阻状态之一。 保险丝盒包括至少一个电熔丝，串联耦合到电熔丝的编程装置，以及耦合到保险丝盒并配置成产生两个或多个电压电平的可变电源。

公开(公告)号：US08358165B2

公开(公告)日：2013-01-22

申请号：US13308035

申请日：2011-11-30

Applicant: Shao-Yu Chou ,  Yen-Huei Chen ,  Jui-Jen Wu

Inventor： Shao-Yu Chou ,  Yen-Huei Chen ,  Jui-Jen Wu

IPC: H03L5/00

CPC classification number: H03K3/356113 ,  H03K3/356182

Abstract: A voltage level shifter having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) includes a first PMOS transistor and a second PMOS transistor each with a source connected to the VCCH, a gate of the first PMOS transistor being coupled to a drain of the second PMOS transistor, and a gate of the second PMOS transistor being coupled to a drain of the first PMOS transistor. The voltage level shifter further includes a first NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, such that the voltage level shifter can operate at a lower VCCL.

Abstract translation: 具有内部低电压电源（VCCL）和外部高压电源（VCCH）的电压电平移位器包括：第一PMOS晶体管和第二PMOS晶体管，每个PMOS晶体管和第二PMOS晶体管的源极连接到VCCH，第一PMOS晶体管的栅极 耦合到第二PMOS晶体管的漏极，并且第二PMOS晶体管的栅极耦合到第一PMOS晶体管的漏极。 电压电平移位器还包括第一NMOS晶体管，源极连接到地（VSS），栅极连接到在VCCL和VSS之间摆动的第一信号，以及耦合在第一PMOS晶体管的漏极之间的第一阻断装置 以及第一NMOS晶体管的漏极，使得电压电平移位器可以在较低VCCL下工作。

公开(公告)号：US20120306537A1

公开(公告)日：2012-12-06

申请号：US13308035

申请日：2011-11-30

Applicant: Shao-Yu Chou ,  Yen-Huei Chen ,  Jui-Jen Wu

Inventor： Shao-Yu Chou ,  Yen-Huei Chen ,  Jui-Jen Wu

IPC: H03K19/0175

CPC classification number: H03K3/356113 ,  H03K3/356182

Abstract: A voltage level shifter having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) includes a first PMOS transistor and a second PMOS transistor each with a source connected to the VCCH, a gate of the first PMOS transistor being coupled to a drain of the second PMOS transistor, and a gate of the second PMOS transistor being coupled to a drain of the first PMOS transistor. The voltage level shifter further includes a first NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, such that the voltage level shifter can operate at a lower VCCL.

Abstract translation: 具有内部低电压电源（VCCL）和外部高压电源（VCCH）的电压电平移位器包括：第一PMOS晶体管和第二PMOS晶体管，每个PMOS晶体管和第二PMOS晶体管的源极连接到VCCH，第一PMOS晶体管的栅极 耦合到第二PMOS晶体管的漏极，并且第二PMOS晶体管的栅极耦合到第一PMOS晶体管的漏极。 电压电平移位器还包括第一NMOS晶体管，源极连接到地（VSS），栅极连接到在VCCL和VSS之间摆动的第一信号，以及耦合在第一PMOS晶体管的漏极之间的第一阻断装置 以及第一NMOS晶体管的漏极，使得电压电平移位器可以在较低VCCL下工作。

公开(公告)号：US08179735B2

公开(公告)日：2012-05-15

申请号：US12732931

申请日：2010-03-26

Applicant: Jui-Jen Wu

Inventor： Jui-Jen Wu

IPC: G11C7/00

CPC classification number: G11C7/12 ,  G11C7/08 ,  G11C7/18 ,  G11C8/14 ,  G11C11/413 ,  G11C2207/002 ,  G11C2207/005

Abstract: In some embodiments related to reading data in a memory cell, the data is driven to a local bit line, which drives a local sense amplifier. Depending on the logic level of the data in the memory cell and thus the local bit line, the local sense amplifier transfers the data on the local bit line to a global bit line. A neighbor global bit line is used as a reference for a global sense amplifier to read the differential data on the global bit line and the neighbor global bit line.

Abstract translation: 在与存储器单元中读取数据相关的一些实施例中，数据被驱动到驱动局部读出放大器的局部位线。 根据存储器单元中的数据的逻辑电平以及局部位线，局部读出放大器将局部位线上的数据传送到全局位线。 相邻全局位线用作全局读出放大器的参考，以读取全局位线和邻近全局位线上的差分数据。

公开(公告)号：US08144501B2

公开(公告)日：2012-03-27

申请号：US12345125

申请日：2008-12-29

Applicant: Yen-Huei Chen ,  Jui-Jen Wu

Inventor： Yen-Huei Chen ,  Jui-Jen Wu

IPC: G11C11/00

CPC classification number: G11C11/412 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/7855

Abstract: An integrated circuit structure includes a static random access memory (SRAM) cell. The SRAM cell includes a pull-up transistor and a pull-down transistor forming an inverter with the pull-up transistor. The pull-down transistor includes a front gate connected to a gate of the pull-up transistor, and a back-gate decoupled from the front gate.

Abstract translation: 集成电路结构包括静态随机存取存储器（SRAM）单元。 SRAM单元包括上拉晶体管和下拉晶体管，其形成具有上拉晶体管的反相器。 下拉晶体管包括连接到上拉晶体管的栅极的前栅极和从前栅极去耦的后栅极。

公开(公告)号：US07466581B2

公开(公告)日：2008-12-16

申请号：US11713280

申请日：2007-03-02

Applicant: Huai-Ying Huang ,  Yen-Huei Chen ,  Jui-Jen Wu ,  Ping-Wei Wang

Inventor： Huai-Ying Huang ,  Yen-Huei Chen ,  Jui-Jen Wu ,  Ping-Wei Wang

IPC: G11C11/00

CPC classification number: G11C11/413

Abstract: An array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns includes a plurality of VSS lines connected to VSS nodes of the SRAM cells, with each VSS line connected to the SRAM cells in a same column. The plurality of VSS lines includes a first VSS line connected to a first column of the SRAM cells; and a second VSS line connected to a second column of the SRAM cells, wherein the first and the second VSS lines are disconnected from each other.

公开(公告)号：US20080212353A1

公开(公告)日：2008-09-04

申请号：US11713280

申请日：2007-03-02

Applicant: Huai-Ying Huang ,  Yen-Huei Chen ,  Jui-Jen Wu ,  Ping-Wei Wang

Inventor： Huai-Ying Huang ,  Yen-Huei Chen ,  Jui-Jen Wu ,  Ping-Wei Wang

IPC: G11C5/06

CPC classification number: G11C11/413

Abstract: An array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns includes a plurality of VSS lines connected to VSS nodes of the SRAM cells, with each VSS line connected to the SRAM cells in a same column. The plurality of VSS lines includes a first VSS line connected to a first column of the SRAM cells; and a second VSS line connected to a second column of the SRAM cells, wherein the first and the second VSS lines are disconnected from each other.

Abstract translation: 布置在多行和多列中的静态随机存取存储器（SRAM）单元的阵列包括连接到SRAM单元的VSS节点的多条VSS线，每条VSS线连接到同一列中的SRAM单元 。 多个VSS线包括连接到SRAM单元的第一列的第一VSS线; 以及连接到所述SRAM单元的第二列的第二VSS线，其中所述第一和第二VSS线彼此断开。

公开(公告)号：US20080184064A1

公开(公告)日：2008-07-31

申请号：US11669667

申请日：2007-01-31

Applicant: Jui-Jen Wu ,  Yung-Lung Lin ,  Yen-Huei Chen ,  Dao-Ping Wang

Inventor： Jui-Jen Wu ,  Yung-Lung Lin ,  Yen-Huei Chen ,  Dao-Ping Wang

IPC: G06F11/16

CPC classification number: G11C29/808

Abstract: The disclosure generally relates to a method and apparatus for a high efficiency redundancy scheme for a memory system. In one embodiment, the disclosure relates to a memory circuit having: a memory array defined by a plurality of memory cells arranged in one or more columns and one or more rows, each memory cell communicating with one of a pair of complementary bit-lines and with a word-line; a plurality of IO circuits, each IO circuit associated with one of the plurality of memory cell columns; a plurality of redundant bit-lines, each redundant bit line communicating with a redundant bit cell; a first circuit for detecting a defective memory cell in said memory circuit; a second circuit for selecting one of the plurality of redundant bit-lines for switching from the failed memory cell to the redundant memory cell; and a third circuit for directing a word-line pulse of said defective memory cell to said selected redundant memory cell.

Abstract translation: 本公开一般涉及用于存储器系统的高效冗余方案的方法和装置。 在一个实施例中，本公开涉及一种存储器电路，其具有：由多个存储单元限定的存储器阵列，所述多个存储器单元被布置成一列或多列和一行或多行，每个存储器单元与一对互补位线中的一个通信， 用字线; 多个IO电路，与所述多个存储单元列之一相关联的每个IO电路; 多个冗余位线，每个冗余位线与冗余位单元通信; 用于检测所述存储器电路中的有缺陷的存储单元的第一电路; 用于选择所述多个冗余位线中的一个用于从所述故障存储器单元切换到所述冗余存储器单元的第二电路; 以及用于将所述有缺陷的存储器单元的字线脉冲引导到所述选择的冗余存储单元的第三电路。

公开(公告)号：US20070159231A1

公开(公告)日：2007-07-12

申请号：US11328780

申请日：2006-01-10

Applicant: Yung-Lung Lin ,  Jui-Jen Wu ,  Hung-Jen Liao

Inventor： Yung-Lung Lin ,  Jui-Jen Wu ,  Hung-Jen Liao

IPC: H01H37/76

CPC classification number: G11C11/56 ,  G11C17/18

Abstract: An integrated circuit for programming an electrical fuse includes a first programming device coupled to the electrical fuse for selectively providing the same with a first programming current, and a second programming device coupled to the electrical fuse for selectively providing the same with a second programming current. A detection module is coupled to the electrical fuse for generating an output indicating a resistance level of the electrical fuse, wherein the resistance level has three or more predetermined states, which are provided by selectively programming the electrical fuse with the first or second programming current.