公开(公告)号：US07183202B2

公开(公告)日：2007-02-27

申请号：US10989668

申请日：2004-11-17

Applicant: Sang-Jin Lee ,  Kyung-Tae Lee ,  Byung-Jun Oh

Inventor： Sang-Jin Lee ,  Kyung-Tae Lee ,  Byung-Jun Oh

IPC: H01L21/4763

CPC classification number: H01L21/76808 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming metal wiring in a semiconductor device is disclosed. The method uses a dual damascene process in which a trench is formed prior to a via-hole.

Abstract translation: 公开了一种在半导体器件中形成金属布线的方法。 该方法使用双镶嵌工艺，其中在通孔之前形成沟槽。

公开(公告)号：US07030022B2

公开(公告)日：2006-04-18

申请号：US10655423

申请日：2003-09-04

Applicant: Mu-kyoung Jung ,  Kyung-tae Lee

Inventor： Mu-kyoung Jung ,  Kyung-tae Lee

IPC: H01L21/302

CPC classification number: H01L21/76838 ,  H01L21/3212 ,  H01L21/76816 ,  H01L23/5222 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of manufacturing a semiconductor device having a first region, in which a capacitance component is a dominant cause of a RC delay, and a second region, in which a resistance component is a dominant cause of a RC delay. The method comprises performing a first etching process to an insulating layer formed on a semiconductor substrate, so that a first trench having a first thickness and a second trench having the first thickness are formed in the first region and the second region, respectively; performing a second etching process to the second trench, so that a third trench having a second thickness thicker than the first thickness is formed in the second region; filling the first trench and the third trench with a metal layer; and removing portions of the metal layer, so that a first metal interconnection and a second metal interconnection are formed inside of the first trench and the third trench, respectively.

Abstract translation: 提供一种制造半导体器件的方法，该半导体器件具有其中电容分量是RC延迟的主要原因的第一区域和其中电阻分量是RC延迟的主要原因的第二区域。 该方法包括对形成在半导体衬底上的绝缘层进行第一蚀刻处理，使得具有第一厚度的第一沟槽和具有第一厚度的第二沟槽分别形成在第一区域和第二区域中; 对所述第二沟槽进行第二蚀刻处理，使得在所述第二区域中形成具有比所述第一厚度更厚的第二厚度的第三沟槽; 用金属层填充第一沟槽和第三沟槽; 以及去除金属层的部分，使得分别在第一沟槽和第三沟槽内部形成第一金属互连和第二金属互连。

公开(公告)号：US20050029010A1

公开(公告)日：2005-02-10

申请号：US10891062

申请日：2004-07-15

Applicant: Jeong-hoon Ahn ,  Hyo-jong Lee ,  Kyung-tae Lee ,  Kyoung-woo Lee ,  Soo-geun Lee ,  Bong-seok Suh

Inventor： Jeong-hoon Ahn ,  Hyo-jong Lee ,  Kyung-tae Lee ,  Kyoung-woo Lee ,  Soo-geun Lee ,  Bong-seok Suh

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/4763 ,  H01L23/52 ,  H05K1/11

CPC classification number: H01L21/76877 ,  H01L21/76847

Abstract: A metal interconnection structure includes a lower metal interconnection layer disposed in a first inter-layer dielectric layer. An inter-metal dielectric layer having a via contact hole that exposes a portion of surface of the lower metal layer pattern is disposed on the first inter-layer dielectric layer and the lower metal layer pattern. A second inter-layer dielectric layer having a trench that exposes the via contact hole is formed on the inter-metal dielectric layer. A barrier metal layer is formed on a vertical surface of the via contact and the exposed surface of the second lower metal interconnection layer pattern. A first upper metal interconnection layer pattern is disposed on the barrier metal layer, thereby filling the via contact hole and a portion of the trench. A void diffusion barrier layer is disposed on the first metal interconnection layer pattern and a second upper metal interconnection layer pattern is disposed on the void diffusion barrier layer to completely fill the trench.

Abstract translation: 金属互连结构包括设置在第一层间电介质层中的下金属互连层。 具有暴露下部金属层图案的一部分表面的通孔接触孔的金属间介电层设置在第一层间电介质层和下部金属层图案上。 在金属间电介质层上形成具有暴露通孔接触孔的沟槽的第二层间电介质层。 在通孔接触件的垂直表面和第二下部金属互连层图案的暴露表面上形成阻挡金属层。 第一上金属互连层图案设置在阻挡金属层上，从而填充通孔接触孔和沟槽的一部分。 空隙扩散阻挡层设置在第一金属互连层图案上，并且第二上金属互连层图案设置在空隙扩散阻挡层上以完全填充沟槽。