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    SMART SOFT COMPOSITE ACTUATOR
    2.
    发明申请
    SMART SOFT COMPOSITE ACTUATOR 审中-公开
    智能柔软的复合致动器

    公开(公告)号：US20150001994A1

    公开(公告)日：2015-01-01

    申请号：US14346682

    申请日：2012-01-25

    申请人： Sung Hoon Ahn ,  Hyung Jung Kim ,  Gil Yong Lee ,  Kyung Tae Lee ,  Renzhe Wu ,  Ji Soo Kim ,  Sung Hyuk Song

    发明人： Sung Hoon Ahn ,  Hyung Jung Kim ,  Gil Yong Lee ,  Kyung Tae Lee ,  Renzhe Wu ,  Ji Soo Kim ,  Sung Hyuk Song

    IPC分类号： H01L41/18

    CPC分类号： H01L41/0966 ,  F03G7/065 ,  H01L41/094 ,  H01L41/096

    摘要： Disclosed is a smart soft composite actuator which enables user-desiring deformation by changing the position of smart material functioning as an active component, wherein the smart soft composite actuator comprises a smart material whose shape is changeable based on an external signal; and a matrix for supporting the smart material and determining an external shape, wherein the smart material is positioned inside the matrix or in a surface of the matrix, and at least one of in-plane shear deformation and out-of-plane deformation is realized by controlling the position of smart material.

    摘要翻译： 公开了一种智能软复合致动器，其通过改变用作有源部件的智能材料的位置来实现用户期望的变形，其中智能软复合致动器包括其形状可基于外部信号而变化的智能材料; 以及用于支撑所述智能材料并确定外部形状的矩阵，其中所述智能材料位于所述基体内或所述基体的表面内，并且实现面内剪切变形和平面外变形中的至少一个 通过控制智能材料的位置。

    Void boundary structures, semiconductor devices having the void boundary structures and methods of forming the same
    3.
    发明申请
    Void boundary structures, semiconductor devices having the void boundary structures and methods of forming the same 有权
    空隙边界结构，具有空隙边界结构的半导体器件及其形成方法

    公开(公告)号：US20080042268A1

    公开(公告)日：2008-02-21

    申请号：US11730276

    申请日：2007-03-30

    申请人： Cheong-Sik Yu ,  Kyung-Tae Lee

    发明人： Cheong-Sik Yu ,  Kyung-Tae Lee

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L23/5222 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76834 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Void boundary structures, semiconductor devices having the void boundary structures, and methods of forming the same are provided. The structures, semiconductor devices and methods present a way for reducing parasitic capacitance between interconnections by forming a void between the interconnections. The interconnections may be formed on a semiconductor substrate. An upper width of each of the interconnections may be wider than a lower width thereof. A molding layer encompassing the interconnections may be formed. A void boundary layer covering the molding layer may be formed to define the void between the interconnections.

    摘要翻译： 提供空隙边界结构，具有空隙边界结构的半导体器件及其形成方法。 结构，半导体器件和方法通过在互连之间形成空隙来提供减少互连之间的寄生电容的方法。 互连可以形成在半导体衬底上。 每个互连的上部宽度可以比其较低的宽度宽。 可以形成包含互连的成型层。 可以形成覆盖模制层的空隙边界层以限定互连之间的空隙。

    Capacitor having high electrostatic capacity, integrated circuit device including the capacitor and method of fabricating the same
    4.
    发明申请
    Capacitor having high electrostatic capacity, integrated circuit device including the capacitor and method of fabricating the same 有权
    具有高静电容量的电容器，包括电容器的集成电路器件及其制造方法

    公开(公告)号：US20070200159A1

    公开(公告)日：2007-08-30

    申请号：US11706972

    申请日：2007-02-16

    申请人： Byung-jun Oh ,  Kyung-tae Lee ,  Yoon-hae Kim

    发明人： Byung-jun Oh ,  Kyung-tae Lee ,  Yoon-hae Kim

    IPC分类号： H01L29/94

    CPC分类号： H01L23/5223 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A capacitor may include a first electrode, a second electrode, a low dielectric layer, and/or a high dielectric layer. The first electrode may include at least one first electrode branch. The second electrode may face the first electrode and include at least one second electrode branch. The low dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may have a higher dielectric constant than the low dielectric layer.

    摘要翻译： 电容器可以包括第一电极，第二电极，低介电层和/或高电介质层。 第一电极可以包括至少一个第一电极分支。 第二电极可面向第一电极并且包括至少一个第二电极分支。 低电介质层可以形成在第一电极分支和第二电极分支之间。 高电介质层可以形成在第一电极分支和第二电极分支之间。 高介电层可以具有比低介电层更高的介电常数。

    Integrated Circuit Devices Including A Capacitor
    5.
    发明申请
    Integrated Circuit Devices Including A Capacitor 有权
    包括电容器的集成电路器件

    公开(公告)号：US20070145452A1

    公开(公告)日：2007-06-28

    申请号：US11684865

    申请日：2007-03-12

    申请人： Byung-jun Oh ,  Kyung-tae Lee ,  Mu-kyeng Jung

    发明人： Byung-jun Oh ,  Kyung-tae Lee ,  Mu-kyeng Jung

    IPC分类号： H01L29/94

    CPC分类号： H01L21/76801 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer. A second conductive interconnection layer is provided in the at least one via hole of the second intermetal dielectric layer that electrically contacts the first conductive interconnection layer.

    摘要翻译： 集成电路器件包括集成电路衬底和集成电路衬底上的电容器的导电下电极层。 介电层位于下电极层上，电容器的导电上电极层位于电介质层上。 第一金属间电介质层在上电极层上。 第一金属间电介质层包括延伸到上电极层的至少一个通孔。 第一导电互连层位于第一金属间电介质层的至少一个通孔上。 第二金属间介电层位于第一金属间电介质层上。 第二金属间电介质层包括延伸到第一导电互连层并且至少部分暴露第一金属间介电层的至少一个通孔的至少一个通孔。 第二导电互连层设置在与第一导电互连层电接触的第二金属间电介质层的至少一个通孔中。

    Semiconductor memory devices and methods of fabricating the same
    6.
    发明申请
    Semiconductor memory devices and methods of fabricating the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20070035028A1

    公开(公告)日：2007-02-15

    申请号：US11499059

    申请日：2006-08-04

    申请人： Young-woo Cho ,  Kyung-tae Lee ,  Heon-jong Shin ,  Young-hwan Oh

    发明人： Young-woo Cho ,  Kyung-tae Lee ,  Heon-jong Shin ,  Young-hwan Oh

    IPC分类号： H01L23/52

    CPC分类号： H01L27/1104 ,  H01L21/76808 ,  H01L27/0207 ,  H01L27/11

    摘要： Integrated circuit memory devices include an integrated circuit substrate and a plurality of lower wiring lines on the substrate and extending in a first direction. An interlayer insulating layer is on the plurality of lower wiring lines. An upper damascene wiring line is in an upper portion of the interlayer insulating layer and extending in a second direction, different from the first direction, to extend over the plurality of lower wiring lines. The upper damascene wiring line has protruded regions extending therefrom in a direction different from the second direction, the protruded regions extending over respective underlying ones of the lower wiring lines. A first via extends through the interlayer insulating layer under a first of the protruded regions and connects the upper damascene wiring line to a corresponding underlying first one of the plurality of wiring lines. A second via extends through the interlayer insulating layer under a second of the protruded regions and connects the upper damascene wiring line to a corresponding underlying second one of the plurality of wiring lines.

    摘要翻译： 集成电路存储器件包括集成电路基板和在基板上的多个下布线，并沿第一方向延伸。 层间绝缘层位于多个下布线上。 上部镶嵌线路位于层间绝缘层的上部，并且沿与第一方向不同的第二方向延伸，在多条下部布线上延伸。 上部镶嵌线具有沿与第二方向不同的方向从其延伸的突出区域，突出区域延伸到下部布线的下方。 第一通孔延伸穿过位于第一突出区域的层间绝缘层，并将上镶嵌布线连接到多个布线中相应的下面的第一布线。 第二通孔在第二突出区域的下方延伸穿过层间绝缘层，并将上部镶嵌线路连接到多条布线中相应的下面的第二布线。

    Metal-insulator-metal capacitors and methods of forming the same
    7.
    发明申请
    Metal-insulator-metal capacitors and methods of forming the same 审中-公开
    金属绝缘体金属电容器及其形成方法

    公开(公告)号：US20060183280A1

    公开(公告)日：2006-08-17

    申请号：US11352660

    申请日：2006-02-13

    申请人： Sang-Jin Lee ,  Young-Joon Moon ,  Seung-Koo Lee ,  Kyung-Tae Lee

    发明人： Sang-Jin Lee ,  Young-Joon Moon ,  Seung-Koo Lee ,  Kyung-Tae Lee

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/76816 ,  H01L21/76807 ,  H01L28/60

    摘要： There are provided metal-insulator-metal (MIM) capacitors and methods of forming the same. The capacitors and the formation methods thereof provide a way of simplifying semiconductor fabrication processes, using component elements of the capacitor and insulating layers around the capacitor. To this end, lower and upper electrodes are sequentially stacked on a semiconductor substrate. A dielectric layer pattern is interposed between the upper and lower electrodes. An etch stop layer pattern and an etch buffer layer are disposed on the upper electrode and under the lower electrode, respectively. The upper and lower electrodes are disposed to expose the dielectric layer pattern and the etch buffer layer.

    摘要翻译： 提供金属 - 绝缘体 - 金属（MIM）电容器及其形成方法。 电容器及其形成方法提供了使用电容器的元件和电容器周围的绝缘层来简化半导体制造工艺的方法。 为此，下电极和上电极依次堆叠在半导体衬底上。 电介质层图案插入在上电极和下电极之间。 蚀刻停止层图案和蚀刻缓冲层分别设置在上电极和下电极下。 上电极和下电极被设置为暴露电介质层图案和蚀刻缓冲层。

    Void-free metal interconnection structure and method of forming the same
    8.
    发明授权
    Void-free metal interconnection structure and method of forming the same 有权
    无孔金属互连结构及其形成方法

    公开(公告)号：US06953745B2

    公开(公告)日：2005-10-11

    申请号：US10891062

    申请日：2004-07-15

    申请人： Jeong-hoon Ahn ,  Hyo-jong Lee ,  Kyung-tae Lee ,  Kyoung-woo Lee ,  Soo-geun Lee ,  Bong-seok Suh

    发明人： Jeong-hoon Ahn ,  Hyo-jong Lee ,  Kyung-tae Lee ,  Kyoung-woo Lee ,  Soo-geun Lee ,  Bong-seok Suh

    IPC分类号： H01L21/768 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/4763 ,  H01L23/52 ,  H05K1/11

    CPC分类号： H01L21/76877 ,  H01L21/76847

    摘要： A metal interconnection structure includes a lower metal interconnection layer disposed in a first inter-layer dielectric layer. An inter-metal dielectric layer having a via contact hole that exposes a portion of surface of the lower metal layer pattern is disposed on the first inter-layer dielectric layer and the lower metal layer pattern. A second inter-layer dielectric layer having a trench that exposes the via contact hole is formed on the inter-metal dielectric layer. A barrier metal layer is formed on a vertical surface of the via contact and the exposed surface of the second lower metal interconnection layer pattern. A first upper metal interconnection layer pattern is disposed on the barrier metal layer, thereby filling the via contact hole and a portion of the trench. A void diffusion barrier layer is disposed on the first metal interconnection layer pattern and a second upper metal interconnection layer pattern is disposed on the void diffusion barrier layer to completely fill the trench.

    摘要翻译： 金属互连结构包括设置在第一层间电介质层中的下金属互连层。 具有暴露下部金属层图案的一部分表面的通孔接触孔的金属间介电层设置在第一层间电介质层和下部金属层图案上。 在金属间电介质层上形成具有暴露通孔接触孔的沟槽的第二层间电介质层。 在通孔接触件的垂直表面和第二下部金属互连层图案的暴露表面上形成阻挡金属层。 第一上金属互连层图案设置在阻挡金属层上，从而填充通孔接触孔和沟槽的一部分。 空隙扩散阻挡层设置在第一金属互连层图案上，并且第二上金属互连层图案设置在空隙扩散阻挡层上以完全填充沟槽。