公开(公告)号：US20210124641A1

公开(公告)日：2021-04-29

申请号：US16678810

申请日：2019-11-08

Applicant: Microchip Technology Inc.

Inventor： Robert E. Caldwell, JR.

IPC: G06F11/10 ,  G06F3/06 ,  G11B20/12

Abstract: A method for operating a storage controller to write to a group of multi-actuator disk drives includes receiving a data stream, performing RAID mapping to a preselected RAID level, organizing the data stream into at least one data stream, creating at least one parity data stream, organizing each data stream and parity data stream into blocks of data, dividing each data stream and each parity data stream into groups of blocks of data assigned to a logical unit representing a drive and an actuator, blocks of data from a data stream and parity stream assigned to a different drive, sequential groups of blocks of data assigned substantially equally to logical units representing actuators in each drive, providing each group of blocks of data to a target port associated with the drive to which it has been assigned, and sending each group of blocks of data from the target port.

公开(公告)号：US20210111082A1

公开(公告)日：2021-04-15

申请号：US16816010

申请日：2020-03-11

Applicant: Microchip Technology Inc.

Inventor： Matthias Klein ,  Andreas Zakrzewski ,  Richard Gruenwald

IPC: H01L23/16 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: A packaged electronic die having a micro-cavity and a method for forming a packaged electronic die. The packaged electronic die includes a photoresist frame secured to the electronic die and extending completely around the device. The photoresist frame is further secured to a first major surface of a substrate so as to form an enclosure around the device. Encapsulant material extends over the electronic die and around the sides of the electronic die. The encapsulant material is in contact with the first major surface of the substrate around the entire periphery of the electronic die so as to form a seal around the electronic die.

公开(公告)号：US20210058496A1

公开(公告)日：2021-02-25

申请号：US16562994

申请日：2019-09-06

Applicant: Microchip Technology Inc.

Inventor： Winston MOK ,  Steven Scott GORSHE

IPC: H04L29/06 ,  H04L29/08

Abstract: A method for extracting path overhead (POH) data blocks from a data stream in a 64B/66B-block communication link, the method includes receiving at a sink node a data stream in a 64B/66B-block communication link, detecting within the data stream at a PCS sublayer a micro-packet starting with an /S/ control block, including K POH data blocks, and ending with a /T/ control block, extracting the micro-packet from the data stream, and extracting the POH data blocks from the micro-packet.

公开(公告)号：US20210028795A1

公开(公告)日：2021-01-28

申请号：US16790547

申请日：2020-02-13

Applicant: Microchip Technology Inc.

Inventor： Peter John Waldemar Graumann

IPC: H03M13/11 ,  H03M13/41 ,  H03M13/43 ,  H03M13/25 ,  H03M13/01 ,  G06F11/10

Abstract: A method and apparatus for decoding are disclosed. The method includes receiving a first Forward Error Correction (FEC) block of read values, starting a hard-decode process in which a number of check node failures is identified and, during the hard-decode process comparing the identified number of check node failures to a decode threshold. When the identified number of check node failures is not greater than the decode threshold the hard-decode process is continued. When the identified number of check node failures is greater than the decode threshold, the method includes: stopping the hard-decode process prior to completion of the hard-decode process; generating output indicating that additional reads are required; receiving one or more additional FEC blocks of read values, mapping the first FEC block of read values and the additional FEC blocks of read values into soft-input values; and performing a soft-decode process on the soft-input values.

公开(公告)号：US20200327938A1

公开(公告)日：2020-10-15

申请号：US16405936

申请日：2019-05-07

Applicant: Microchip Technology Inc.

Inventor： Fengliang Xue ,  Fethi Dhaoui ,  Victor Nguyen ,  John L. McCollum

IPC: G11C13/00

Abstract: A method for programming a resistive random-access memory (ReRAM) cell includes passing a first current through the ReRAM device for a first period of time, the first current selected to create a leakage path through the ReRAM device, and after passing the first current through the ReRAM device passing a second current through the ReRAM device for a second period of time shorter than the first period of time, the second current selected to create a current path having a desired resistance through the leakage path through the ReRAM device.

公开(公告)号：US10797816B1

公开(公告)日：2020-10-06

申请号：US16446576

申请日：2019-06-19

Applicant: Microchip Technology Inc.

Inventor： Steven Scott Gorshe ,  Winston Mok

IPC: H04B10/516 ,  H04J3/16 ,  H04L12/26 ,  H04Q11/00 ,  H04L12/721

Abstract: A method for extracting POH data blocks and a MOS control block from a data stream in a 64B/66B-block communication link including receiving a data stream, finding a first combination of a MOS control block and K POH data blocks including CRC data in the data stream, extracting the MOS control block and the K POH data blocks from the data stream, searching in a window for a subsequent combination of a MOS control block and K POH data blocks and removing them if at least one of them are found, if neither the subsequent MOS control block nor the K POH data blocks are found within the predetermined window, extracting from the data stream K+1 64B/66B-blocks in the predetermined window.

公开(公告)号：US10735004B1

公开(公告)日：2020-08-04

申请号：US16408096

申请日：2019-05-09

Applicant: Microchip Technology Inc.

Inventor： Matthew Kian Chin Yap ,  Alan Nakamoto

IPC: H03K19/20 ,  H01J37/30 ,  H03K19/17748 ,  H03K19/17728

Abstract: An integrated circuit includes a plurality of logic function circuits disposed on the integrated circuit and interconnected by metal interconnect lines to form a logic network. A plurality of configurable logic function circuits is also disposed on the integrated circuit, each configurable logic function circuit being disposed on a respective area on the integrated circuit and not interconnected by the metal interconnect lines to form the logic network.

公开(公告)号：US09866101B2

公开(公告)日：2018-01-09

申请号：US14984676

申请日：2015-12-30

Applicant: Microchip Technology Inc.

Inventor： Marc Tan ,  Alexander Mednik ,  Simon Krugly ,  Wilson Wai-Sum Chan

IPC: H02M3/158 ,  H02M1/08 ,  H02M1/00 ,  H02M1/36

CPC classification number: H02M1/08 ,  H02M1/36 ,  H02M3/158 ,  H02M2001/0006 ,  H02M2001/0045

Abstract: The invention relates to methods for supplying current to an auxiliary power supply for the control circuit of a switching regulator. The auxiliary power supply is connected in parallel to a first switch of the switching regulator. The auxiliary power supply comprises a second switch. During the nonswitching stage of the switching regulator, the second switch has significant impedance so as to power up the auxiliary power supply gradually and to suppress the flow of large or oscillatory currents which may cause damage or create interference. During the switching stage of the switching regulator, the second switch has negligible impedance so as to avoid undue dissipation within the path for the supply of current.

公开(公告)号：US20160191036A1

公开(公告)日：2016-06-30

申请号：US14919000

申请日：2015-10-21

Applicant: Microchip Technology Inc.

Inventor： Isaac Ko ,  Ka Wai Ho ,  Wan Tim Chan ,  Jimes Lei

IPC: H03K17/06 ,  A61B8/00

CPC classification number: H03K17/063 ,  A61B8/4444 ,  H03K17/693 ,  H03K2217/0009

Abstract: Described herein are multiple designs for an improved analog switch for use in transmitting high voltage signals without using high voltage power supplies for the switch. The analog switches are able to pass and block input signals in the approximate range of −100V to +100V. The use of translinear loops and a bootstrap configuration results in a constant on-resistance of the symmetrical switches and matches the conductance of each analog switch to the transconductance of an NMOS transistor, which can be easily stabilized with a constant gm biasing scheme. In certain embodiments, a shunt termination (T-switch) configuration is used for better off-isolation, and each of the symmetrical switches has its own translinear loop and thus flexibility of on-resistance and termination voltage.

Abstract translation: 这里描述了用于在不使用用于开关的高压电源的情况下传输高电压信号的改进的模拟开关的多种设计。 模拟开关能够通过和阻止输入信号在-100V至+ 100V的近似范围内。 使用跨线性回路和自举配置导致对称开关的导通电阻恒定，并将每个模拟开关的电导与NMOS晶体管的跨导相匹配，这可以通过恒定的gm偏置方案进行稳定。 在某些实施例中，分流端接（T开关）配置用于更好的非隔离，并且每个对称开关具有其自己的横向线性环路，并因此具有导通电阻和终止电压的灵活性。

公开(公告)号：US20160118874A1

公开(公告)日：2016-04-28

申请号：US14984676

申请日：2015-12-30

Applicant: Microchip Technology Inc.

Inventor： Marc Tan ,  Alexander Mednik ,  Simon Krugly ,  Wilson Wai-Sum Chan

IPC: H02M1/08 ,  H02M1/36

CPC classification number: H02M1/08 ,  H02M1/36 ,  H02M3/158 ,  H02M2001/0006 ,  H02M2001/0045

Abstract: The invention relates to methods for supplying current to an auxiliary power supply, where the auxiliary supply is connected in parallel to a first switch of a switching regulator and the parallel connection of the auxiliary supply comprises a diode and a second switch.

Abstract translation: 本发明涉及向辅助电源供电的方法，其中辅助电源并联连接到开关调节器的第一开关，并且辅助电源的并联连接包括二极管和第二开关。