公开(公告)号：US12125642B2

公开(公告)日：2024-10-22

申请号：US18193653

申请日：2023-03-31

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chien-Chung Wang ,  Hsih-Yang Chiu

IPC: H10B12/00 ,  H01G4/228 ,  H01G13/00 ,  H01L29/94 ,  H01L49/02

CPC classification number: H01G4/228 ,  H01G13/00 ,  H01L28/91 ,  H01L28/92 ,  H01L29/945 ,  H10B12/038 ,  H10B12/37 ,  H10B12/39

Abstract: A method of manufacturing a capacitor structure includes the following. A first, second, third, fourth, fifth, sixth and seventh portions of a contact layer arrange from periphery to center. A first-conductive layer contacting the first portion forms in an opening. A first-dielectric layer contacting the second portion forms on the first-conductive layer. A second-conductive layer forms on the first-dielectric layer. A second-dielectric layer contacting the third portion forms on the second-conductive layer. A third-conductive layer contacting the fourth portion forms on the second-dielectric layer. A third-dielectric layer contacting the fifth portion forms on the third-conductive layer. A fourth-conductive layer contacting the second-conductive layer forms on the third-dielectric layer. A fourth-dielectric layer contacting the sixth portion forms on the fourth-conductive layer. A fifth-conductive layer contacting the seventh portion forms on the fourth-dielectric layer. A fifth-dielectric layer forms on the fourth-dielectric layer and the fifth-conductive layer.

公开(公告)号：US20240347451A1

公开(公告)日：2024-10-17

申请号：US18134529

申请日：2023-04-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： ZIH-HONG YANG

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226

Abstract: An interconnection structure and a method of manufacturing an interconnection structure are provided. The interconnection structure includes a first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and a first conductive layer disposed in the first dielectric layer. The interconnection structure also includes a conductive via electrically connected with the first conductive layer and extending through the first dielectric layer and the second dielectric layer. The conductive via has a first lateral surface surrounded by the first dielectric layer and a second lateral surface surrounded by the second dielectric layer. The first lateral surface and the second lateral surface have different slopes.

公开(公告)号：US20240347378A1

公开(公告)日：2024-10-17

申请号：US18133058

申请日：2023-04-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： YING-CHENG CHUANG

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76802 ,  H01L21/76837 ,  H01L23/5283

Abstract: The present application provides a semiconductor structure and a manufacturing method of the semiconductor structure. A substrate is provided, wherein the substrate includes a plurality of pillars, and a top surface of each of the plurality of pillars is a substantially planar surface. A first oxide layer is formed over the substrate conformal to the pillars, wherein the formation of the first oxide layer includes oxidizing top corners of the pillars, thereby causing the top surface of each of the plurality of pillars to become a convex surface. A first dielectric layer is formed among the pillars, wherein the first oxide layer above the plurality of pillars is partially exposed through the first dielectric layer. A planarization is performed on the pillars to partially or entirely remove the convex surface.

公开(公告)号：US20240341084A1

公开(公告)日：2024-10-10

申请号：US18744946

申请日：2024-06-17

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： CHING-KAI CHUANG

IPC: H10B12/00

CPC classification number: H10B12/37 ,  H10B12/038

Abstract: The present application provides a memory device having a memory cell with reduced protrusion protruding from the memory cell. The memory device includes a semiconductor substrate having a fin portion protruding from a surface of the semiconductor substrate; a semiconductive layer disposed conformal to the fin portion; a conductive layer disposed over the semiconductive layer; an insulating layer disposed over the conductive layer; and a protrusion including a first protruding portion laterally protruding from the semiconductive layer and along the surface, a second protruding portion laterally protruding from the conductive layer and over the first protruding portion, and a third protruding portion laterally protruding from the insulating layer and over the second protruding portion, wherein the protrusion has an undercut profile.

公开(公告)号：US12114476B2

公开(公告)日：2024-10-08

申请号：US18221534

申请日：2023-07-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yuan-Yuan Lin

IPC: H10B12/00

CPC classification number: H10B12/0335 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34

Abstract: A method for preparing the memory are provided. The method includes forming a trench at a front side of a semiconductor substrate, wherein the trench defines laterally separate active areas formed of surface regions of the semiconductor substrate; filling an isolation structure in the trench, wherein the isolation structure is filled to a height lower than top surfaces of the active areas; recessing a first group of the active areas from top surfaces of the first group of the active areas, while having top surfaces of a second group of the active areas covered; and forming contact enhancement sidewall spacers to laterally surround top portions of the active areas, respectively.

公开(公告)号：US12113527B2

公开(公告)日：2024-10-08

申请号：US17886473

申请日：2022-08-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chang-Ting Wu

IPC: H03K19/00 ,  H03K19/0185

CPC classification number: H03K19/0005 ,  H03K19/018557

Abstract: An off-chip driver (OCD), including a pull-up driver and a pull-down driver, is provided. The pull-up driver and the pull-down driver are coupled to an output pad. One of the pull-up driver and the pull-down driver includes a main driving circuit, an auxiliary driving circuit, a connection circuit, and a common impedance. The main driving circuit is used to perform an output driving operation on the output pad, and the auxiliary driving circuit is used to selectively perform the output driving operation on the output pad. A first terminal of the common impedance is coupled to a driving terminal of the main driving circuit and a driving terminal of the auxiliary driving circuit through the connection circuit. A second terminal of the common impedance is coupled to the output pad.

公开(公告)号：US20240332334A1

公开(公告)日：2024-10-03

申请号：US18736847

申请日：2024-06-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： YU-HAN HSUEH

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/1469

Abstract: The present application provides an optical semiconductor device with a composite intervening structure. The optical semiconductor device includes a logic die including a core circuit area and a logic peripheral circuit area; a memory die positioned on the logic die and including a memory cell area and a memory peripheral area, and a first inter-die via positioned in the memory peripheral area and electrically connected to the logic peripheral circuit area; and a sensor die positioned on the memory die and including a sensor pixel area and a sensor peripheral area, a first intra-die via positioned in the sensor peripheral area and electrically coupled to the logic peripheral circuit area through the first inter-die via, and a second intra-die via positioned in the sensor peripheral area. The intervening structure is disposed on the back surface of the memory die.

公开(公告)号：US20240331751A1

公开(公告)日：2024-10-03

申请号：US18193648

申请日：2023-03-31

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shu-Wei Yang

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1093

Abstract: A data strobe latching circuit and an adjusting method for adjusting an internal write latency signal are provided. The DQS latching circuit includes a receiver, a counting circuit and a timing adjusting circuit. The receiver receives a DQS signal. The counting circuit counts at least one pulse of the DQS signal to generate an adjusting value. The timing adjusting circuit adjusts a timing of the internal write latency signal according to the adjusting value.

公开(公告)号：US20240329675A1

公开(公告)日：2024-10-03

申请号：US18190121

申请日：2023-03-27

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jia-Wun Syu

IPC: G05F1/46 ,  G05F1/575

CPC classification number: G05F1/468 ,  G05F1/461 ,  G05F1/575

Abstract: A startup circuit and a bandgap circuit are provided. The startup circuit includes a start referencing circuit and a driving circuit. The start referencing circuit is configured to receive an enabling signal ramping from a disabled voltage level to an enabled voltage level to generate a reference signal. The driving circuit has an input end coupled to the start referencing circuit and an output end coupled to an operational amplifier circuit of the bandgap circuit. The driving circuit is configured to generate a driving signal to the operational amplifier circuit according to the reference signal. The driving circuit comprises a plurality of buffer circuits coupled in series and at least one of the buffer circuits being a hysteresis buffer.

公开(公告)号：US12107002B2

公开(公告)日：2024-10-01

申请号：US18484452

申请日：2023-10-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chuan-Lin Hsiao ,  Wei-Ming Liao

IPC: H01L21/762 ,  H01L29/06 ,  H10B12/00

CPC classification number: H01L21/76237 ,  H01L29/0638 ,  H01L29/0649 ,  H10B12/00

Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.