公开(公告)号：US20080049521A1

公开(公告)日：2008-02-28

申请号：US11844480

申请日：2007-08-24

Applicant: Rino Micheloni ,  Luca Crippa ,  Roberto Ravasio ,  Federico Pio

Inventor： Rino Micheloni ,  Luca Crippa ,  Roberto Ravasio ,  Federico Pio

IPC: G11C16/04

CPC classification number: G11C16/344

Abstract: A method for operating a flash memory device. The memory device includes a matrix of memory cells each one having a programmable threshold voltage defining a value stored in the memory cell. The method includes the steps of erasing a block of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell of the block for writing a target value; restoring the threshold voltage of a subset of the memory cells of the block to the compacting range, the subset including the at least one first memory cell and/or at least one second memory cell of the block being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.

Abstract translation: 一种用于操作闪存设备的方法。 存储器件包括存储器单元矩阵，每个存储器单元具有限定存储在存储器单元中的值的可编程阈值电压。 该方法包括以下步骤：擦除存储器单元块，以及在预定的压缩范围内压缩块的存储单元的阈值电压，其中压缩步骤包括：选择块写入的至少一个第一存储单元 目标值 将块的存储器单元的子集的阈值电压恢复到压缩范围，该子集包括与至少一个第一存储器相邻的块的至少一个第一存储器单元和/或至少一个第二存储器单元 细胞; 并且至少部分地将目标值写入至少一个第一存储单元。

公开(公告)号：US20080049511A1

公开(公告)日：2008-02-28

申请号：US11828716

申请日：2007-07-26

Applicant: LUCA CRIPPA ,  ROBERTO RAVASIO ,  RINO MICHELONI

Inventor： LUCA CRIPPA ,  ROBERTO RAVASIO ,  RINO MICHELONI

IPC: G11C11/34

CPC classification number: G11C16/10 ,  G11C7/18 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427

Abstract: The capacitive coupling between two adjacent bitlines of a NAND memory device may be exploited for boosting the voltage of bitlines that are not to be programmed in order to inhibit program operations on them. The even (odd) bitlines that include cells not to be programmed are biased with a first voltage for inhibiting them from being programmed while the even (odd) bitlines that include cells to be programmed are grounded. The adjacent odd (even) bitlines are biased at the supply voltage or at an auxiliary voltage for boosting the bias voltage of the even (odd) bitlines above the supply voltage. The bias voltage of the even (odd) bitlines that include cells not to be programmed is boosted because of the relevant parasitic coupling capacitances between adjacent bitlines.

Abstract translation: 可以利用NAND存储器件的两个相邻位线之间的电容耦合来升高不被编程的位线的电压，以便禁止对它们的编程操作。 包括不被编程的单元的偶数（奇数）位线用第一电压偏置，以阻止它们被编程，而包括要编程的单元的偶数（奇数）位线接地。 相邻的奇数（偶数）位线在电源电压或辅助电压处偏置，用于将偶数（奇数）位线的偏置电压升高到电源电压以上。 由于相邻位线之间的相关寄生耦合电容，包括不编程单元的偶数（奇数）位线的偏置电压会升高。

公开(公告)号：US20070038852A1

公开(公告)日：2007-02-15

申请号：US11460777

申请日：2006-07-28

Applicant: Angelo Bovino ,  Roberto Ravasio ,  Rino Micheloni

Inventor： Angelo Bovino ,  Roberto Ravasio ,  Rino Micheloni

IPC: G06F15/177 ,  G06F9/24 ,  G06F9/00 ,  G11C16/04 ,  G11C11/34

CPC classification number: G11C11/5621 ,  G11C16/20

Abstract: A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.

Abstract translation: 多级闪存设备允许更快更有效地配置存储器设备的操作参数，以执行存储器的不同功能算法。简化了测试过程中存储器件工作参数的最佳配置的识别 通过在存储器件的每次上电时允许将配置位一次性处理成存储在嵌入式辅助随机存取存储器中的算法友好数据。这通过执行存储在存储器装置中的特定加电算法代码来完成 嵌入式微处理器的辅助只读存储器。

公开(公告)号：US20070030732A1

公开(公告)日：2007-02-08

申请号：US11495876

申请日：2006-07-28

Applicant: Rino Micheloni ,  Luca Crippa ,  Roberto Ravasio

Inventor： Rino Micheloni ,  Luca Crippa ,  Roberto Ravasio

IPC: G11C16/04

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2216/14

Abstract: A method for programming an electrically programmable memory including a plurality of memory cells arranged in individually-selectable memory cell sets each including at least one memory cell. The programming method includes causing the memory cells of a selected memory cells set to be brought into a predetermined, starting programming state. Receiving a target value for the first data bits groups of the memory cells of the selected memory cells set. Receiving a target value for the second data bits groups of the memory cells of the selected memory cells set. After having received the target values of both the first and the second data bits groups, applying to the memory cells of the selected memory cells set a programming sequence adapted to cause the memory cells of the selected memory cells sets to be brought into a target programming state jointly determined by the target values of the first and second data bits groups.

Abstract translation: 一种用于编程电可编程存储器的方法，包括布置在各自包括至少一个存储单元的可单独选择的存储单元组中的多个存储单元。 编程方法包括使所设置的选定存储单元的存储单元进入预定的开始编程状态。 接收所选存储器单元的存储单元的第一数据位组的目标值。 接收所选存储器单元的存储单元的第二数据位组的目标值。 在接收到第一和第二数据位组两者的目标值之后，将所选择的存储器单元的存储单元应用到所设置的编程顺序，以使所选择的存储单元组的存储器单元进入目标编程 状态由第一和第二数据位组的目标值联合确定。

公开(公告)号：US20060010363A1

公开(公告)日：2006-01-12

申请号：US11173896

申请日：2005-06-30

Applicant: Alessia Marelli ,  Roberto Ravasio ,  Rino Micheloni

Inventor： Alessia Marelli ,  Roberto Ravasio ,  Rino Micheloni

IPC: H03M13/00

CPC classification number: H03M13/1555 ,  H03M13/152 ,  H03M13/6561

Abstract: A method for correcting errors in multilevel memories, both of the NAND and of the NOR type provides the use of a BCH correction code made parallel by means of a coding and decoding architecture allowing the latency limits of prior art sequential solutions to be overcome. The method provides a processing with a first predetermined parallelism for the coding step, a processing with a second predetermined parallelism for the syndrome calculation and a processing with a third predetermined parallelism for calculating the error position, each parallelism being defined by a respective integer number being independent from the others.

Abstract translation: 用于校正多电平存储器中的错误的方法，NAND和NOR类型都提供使用通过编码和解码架构并行制作的BCH校正码，从而可以克服现有技术顺序解决方案的等待时间限制。 该方法提供用于编码步骤的第一预定并行度的处理，用于校正子计算的第二预定并行性的处理和用于计算错误位置的第三预定并行度的处理，每个并行性由相应整数定义为 独立于其他人。

公开(公告)号：US20060005109A1

公开(公告)日：2006-01-05

申请号：US11169497

申请日：2005-06-29

Applicant: Alessia Marelli ,  Roberto Ravasio ,  Rino Micheloni

Inventor： Alessia Marelli ,  Roberto Ravasio ,  Rino Micheloni

IPC: H03M13/00

CPC classification number: H03M13/152 ,  H03M13/1575 ,  H03M13/3707 ,  H03M13/6502

Abstract: A method and system for correcting errors in multilevel memories is based upon using a combination of a BCH correction code and a Hamming correction code. The BCH correction code is used for correcting multiple errors, and the Hamming correction code is used for correcting single errors. The Hamming correction code reduces the use of the decoding blocks for the BCH correction codes, which are computationally intensive.

Abstract translation: 用于校正多电平存储器中的错误的方法和系统基于使用BCH校正码和汉明校正码的组合。 BCH校正码用于校正多个错误，汉明校正码用于校正单个错误。 汉明校正码减少了用于计算密集型的BCH校正码的解码块的使用。