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公开(公告)号：US09785165B2
公开(公告)日：2017-10-10
申请号：US15014320
申请日：2016-02-03
Inventor： Sandor Petenyi , Calogero Ribellino
IPC: G05F1/575
CPC classification number: G05F1/575
Abstract: A significant reduction of the amplitude of the transient response is obtained by keeping a low dropout regulator circuit in a closed loop condition. This is achieved by manipulation of the reference voltage level when an open loop condition arises due to a falling input voltage. In this case, the reference voltage level is tracked with the input voltage level, keeping the output voltage regulated. As a consequence, the power pass element of the regulator is not forced into the linear region (in the case of a MOSFET) or deep saturation (in the case of a bipolar transistor).
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42.发明申请METHOD OF PREVENTING INVERSION OF OUTPUT CURRENT FLOW IN A VOLTAGE REGULATOR AND RELATED VOLTAGE REGULATOR 有权在电压调节器和相关电压调节器中防止输出电流反相的方法公开(公告)号：US20150008871A1
公开(公告)日：2015-01-08
申请号：US14320999
申请日：2014-07-01
Inventor： Sandor Petenyi
CPC classification number: G05F1/625 , G05F1/569 , H02H7/1213 , H02J7/0072
Abstract: The reversal of the flow of output current in a voltage regulator is prevented by equipping the voltage regulator of a regulation transistor controlled by an analog voltage control, having its current terminals connected between the control terminal of the fifth transistor power of the regulator and the power supply line or the common ground node of the regulator. The regulation transistor is configured to provide an electrical path of conduction between the control terminal and the power supply line or the ground node and is controlled by an analog voltage control that varies in a continuous manner between a first level, suitable to extinguish the regulation transistor, and a second level suitable for biasing it in an operating condition of deep conduction, as the difference between the supply voltage and the regulated output voltage approaching an offset voltage.
Abstract translation: 通过装配由模拟电压控制器控制的调节晶体管的电压调节器来防止电压调节器中的输出电流的反转，其电流端子连接在调节器的第五晶体管功率的控制端和功率 供电线路或调节器的公共接地节点。 调节晶体管被配置为提供控制端与电源线或接地节点之间的导通电路，并且通过模拟电压控制来控制，该模拟电压控制以连续的方式在适于熄灭调节晶体管的第一电平之间变化 以及适于在深导通的操作条件下偏置它的第二电平，因为电源电压和调节的输出电压之间的差接近偏移电压。
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43.发明申请公开(公告)号：US20130326254A1
公开(公告)日：2013-12-05
申请号：US13904866
申请日：2013-05-29
Inventor： Christophe Lorin , Benedicte Micheau , Roman Prochazka , Vaclav Jelen , Ondrej Plachy
IPC: G06F1/32
CPC classification number: H02J7/0054 , G06F1/266 , G06F1/3203 , G06F1/3215 , G06F1/3234 , G06F1/3246 , G06F1/3287 , H02J7/0047 , H02J7/007 , H02J7/345 , H02J2007/0049 , H02J2007/0062
Abstract: A method of charging a battery of a device using a battery of a computer powered by the battery, in which the procedure is implemented by a circuit independent of the computer's processors. The method includes supplying a power supply voltage, insufficient to charge a battery, to a computer port, as long as a device is detected as connected to the port, controlling the supply of a charging voltage to the port, while supplying charging voltage to the port, detecting an end of charging condition of a battery of the device, and controlling the cutting off of the charging voltage to the port if the end of charging condition is detected, where this condition is determined according to the intensity of a charging current and according to a quantity of electrical charge supplied to the port and/or of a charging period.
Abstract translation: 一种使用由电池供电的计算机的电池对装置的电池进行充电的方法，其中该过程由独立于计算机的处理器的电路实现。 该方法包括向计算机端口提供不足以对电池充电的电源电压，只要检测到设备连接到端口，控制向端口提供充电电压，同时向该端口提供充电电压 端口，检测设备的电池的充电状态的结束，并且如果检测到充电状态的结束，则控制对端口的充电电压的切断，其中该条件根据充电电流的强度确定，并且 根据提供给端口的电量和/或充电期间。
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公开(公告)号：US20240125930A1
公开(公告)日：2024-04-18
申请号：US18377893
申请日：2023-10-09
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics Design and Application S.R.O. , STMicroelectronics (Alps) SAS
Inventor： Robin VASSAL , Jiri ANDRLE , Peter CABAJ , Cyrille TROUILLEAU
Abstract: A method is for detecting one or more objects in a detection zone using a time-of-flight sensor. The method includes emitting optical radiation via the emission circuitry of the sensor and subsequently capturing the reflected optical radiation using the reception circuitry. This captured radiation is quantified in terms of photons, and measurement circuitry determines both the amount of these photons and the distance from the sensor to the object(s). An analysis of the photon count, combined with the calculated distance, is used to determine the presence or absence of objects within the detection zone.
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公开(公告)号：US11831793B2
公开(公告)日：2023-11-28
申请号：US17107532
申请日：2020-11-30
Inventor： Enrico Rosario Alessi , Mario Antonio Aleo , Karel Blaha , Pavel Vicek
CPC classification number: H04L9/3278 , H02J50/80 , H04W12/71 , H04L2209/805
Abstract: A method for mutual authentication that includes establishing a first inductive coupling between a wireless-power receiver and a wireless-power transmitter to transfer power from the wireless-power transmitter to the wireless-power receiver by a power signal and using the power signal to transmit a first response to a physically unclonable function to the wireless-power transmitter. The method further including generating a second response to the physically unclonable function and communicating information derived from the second response to initiate a mutual authentication process between the wireless-power receiver and the wireless-power transmitter during a subsequent inductive coupling.
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Patent Agency Ranking
公开(公告)号：US11734221B2
公开(公告)日：2023-08-22
申请号：US17199418
申请日：2021-03-11
Inventor： Rolf Nandlinger , Radek Olexa
CPC classification number: G06F13/4291 , G06F9/30134 , G06F13/1673 , G06F13/4031
Abstract: An embodiment processing system comprises a queued SPI circuit, which comprises a hardware SPI communication interface, an arbiter and a plurality of interface circuits. Each interface circuit comprises a transmission FIFO memory, a reception FIFO memory and an interface control circuit. The interface control circuit is configured to receive first data packets and store them to the transmission FIFO memory. The interface control circuit sequentially reads the first data packets from the transmission FIFO memory, extracts at least one transmission data word, and provides the extracted word to the arbiter. The interface control circuit receives from the arbiter a reception data word and stores second data packets comprising the received reception data word to the reception FIFO memory. The interface control circuit sequentially reads the second data packets from the reception FIFO memory and transmits them to the digital processing circuit.
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公开(公告)号：US20230171529A1
公开(公告)日：2023-06-01
申请号：US17537263
申请日：2021-11-29
Inventor： Tomas TEPLY , Karel BLAHA
CPC classification number: H04R1/1025 , H04R9/04 , H04R9/06 , H04R1/1075 , H04R2420/07
Abstract: The present disclosure is directed to a device that includes a headphone speaker housing that includes a coil having a first terminal and a second terminal that is configured to operate in a sound generation mode and a battery charging mode. A class D amplifier circuit is configured to rectify in a battery charging mode and amplify in a sound generation mode, the class D amplifier is coupled to the first terminal and the second terminal of the coil. The class D amplifier including a first, second, third, and fourth switch, the first terminal coupled between the first and second switch, the second terminal coupled between the third and fourth switch. An audio generation circuit having a third terminal and a fourth terminal, the third terminal coupled between the first and third switch of the class D amplifier and the fourth terminal coupled between the second and fourth switch of the class D amplifier. A battery charging circuit coupled to the third terminal and the fourth terminal.
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公开(公告)号：US20220286319A1
公开(公告)日：2022-09-08
申请号：US17677113
申请日：2022-02-22
Inventor： Fred Rennig , Vaclav Dvorak
IPC: H04L12/403 , G06F9/30
Abstract: A circuit includes a first and a second memory, a processor and a timer. The processor generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. The processor stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory. The timer comprises a first register which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter which increases a count number and resets the count number as a function of the value of the first register.
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公开(公告)号：US11366778B2
公开(公告)日：2022-06-21
申请号：US16874055
申请日：2020-05-14
Inventor： Fred Rennig , Ludek Beran
IPC: G06F13/362 , G06F13/40 , G06F11/07 , H04L12/403 , G05B19/042 , H03M13/09
Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
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50.发明申请公开(公告)号：US20220109375A1
公开(公告)日：2022-04-07
申请号：US17490793
申请日：2021-09-30
Inventor： Alberto IORIO , Maurizio FORESTA , Emilio VOLPI , Jan NOVOTNY
IPC: H02M3/335 , G01R19/165 , H02M3/00 , H02M1/00
Abstract: A synchronous rectifier driver circuit is configured to drive a synchronous rectifier FET and includes a first terminal configured to be connected to a source terminal of the synchronous rectifier FET. A second terminal is configured to be connected to a drain terminal of the synchronous rectifier FET, and a third terminal is configured to be connected to a gate terminal of the synchronous rectifier FET. The synchronous rectifier driver circuit is configured to measure the voltage between the second terminal and the first terminal, and detect a switch-on instant in which the measured voltage reaches a first threshold value and a switch-off instant in which the measured voltage reaches a second threshold value. The synchronous rectifier driver circuit generates a drive signal between the third terminal and the first terminal as a function of the measured voltage.
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