公开(公告)号：US20120320700A1

公开(公告)日：2012-12-20

申请号：US13595551

申请日：2012-08-27

Applicant: Sung-Chieh LIN ,  Kuoyuan (Peter) HSU ,  Jiann-Tseng HUANG ,  Wei-Li LIAO

Inventor： Sung-Chieh LIN ,  Kuoyuan (Peter) HSU ,  Jiann-Tseng HUANG ,  Wei-Li LIAO

IPC: G11C5/14 ,  G11C8/00 ,  G11C17/00

CPC classification number: G11C8/12 ,  G11C17/18

Abstract: This description relates to a circuit including a bit line. The circuit further includes at least one memory bank. The at least one memory bank includes at least one memory cell, a first device configured to provide a current path between the bit line and the at least one memory cell when the at least one memory cell is activated, and a second device configured to reduce current leakage between the bit line and the at least one memory cell when the at least one memory cell is deactivated. The circuit further includes a tracking device configured to receive a minor current substantially equal to a current along the current path, the tracking device configured to have a resistance substantially equal to a cumulative resistance of all memory cells of the at least one memory cell.

Abstract translation: 本说明书涉及包括位线的电路。 电路还包括至少一个存储体。 所述至少一个存储体包括至少一个存储器单元，第一器件被配置为当所述至少一个存储器单元被激活时，在所述位线和所述至少一个存储器单元之间提供电流路径，以及被配置为减少 当所述至少一个存储器单元被停用时，所述位线与所述至少一个存储器单元之间的电流泄漏。 电路还包括跟踪装置，其被配置为接收基本上等于沿着电流路径的电流的次要电流，跟踪装置被配置为具有基本上等于至少一个存储器单元的所有存储器单元的累积电阻的电阻。

公开(公告)号：US08270240B2

公开(公告)日：2012-09-18

申请号：US12784025

申请日：2010-05-20

Applicant: Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu ,  Jiann-Tseng Huang ,  We-Li Liao

Inventor： Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu ,  Jiann-Tseng Huang ,  We-Li Liao

IPC: G11C29/00

CPC classification number: G11C8/12 ,  G11C17/18

Abstract: An OTP memory array includes a bit line coupled to a plurality of memory banks. Each memory bank includes a plurality of memory cells, a footer, and a bias device, and is associated with a current mirror. When a memory cell is activated (e.g., for reading) the memory bank including the activated memory cell is referred to as an activated memory bank and other banks are referred to as deactivated memory banks. A current tracking device serves to compensate for bit line leakage current in deactivated memory cells in the activated memory bank. Further, footers and bias devices in deactivated memory banks and associated current mirrors are configured to reduce/eliminate bit line current leakage through deactivated memory cells in deactivated memory banks.

Abstract translation: OTP存储器阵列包括耦合到多个存储体的位线。 每个存储体包括多个存储单元，一个页脚和一个偏置装置，并与一个电流镜相关联。 当存储器单元被激活（例如，用于读取）时，包括激活的存储器单元的存储体被称为激活的存储体，并且其它存储体被称为禁用存储体。 电流跟踪装置用于补偿激活的存储体中的去激活的存储器单元中的位线泄漏电流。 此外，禁用存储器组和相关联的电流镜中的脚和偏置器件被配置为通过去激活的存储体中的去激活的存储器单元来减少/消除位线电流泄漏。

公开(公告)号：US08207783B2

公开(公告)日：2012-06-26

申请号：US12856824

申请日：2010-08-16

Applicant: Wei-Li Liao ,  Sung-Chieh Lin ,  Kuoyuan Hsu

Inventor： Wei-Li Liao ,  Sung-Chieh Lin ,  Kuoyuan Hsu

IPC: H01H37/76

CPC classification number: G11C29/026 ,  G11C29/028

Abstract: An integrated circuit includes a sensing circuit, a fuse box, and a fuse bus decoder. The sensing circuit includes an output node, and the fuse box includes a plurality of switches coupled in series with a plurality of resistive elements. The fuse box is coupled to the output node of the sensing circuit from which the fuse box is configured to receive a current. The fuse bus decoder is coupled to the fuse box and includes at least one demultiplexer configured to receive a signal and in response output a plurality of control signals for selectively opening and closing the switches of the fuse box to adjust a resistance across the fuse box. A voltage of the output node of the sense amplifier is based on a resistance the fuse box and the current.

Abstract translation: 集成电路包括感测电路，保险丝盒和熔丝总线解码器。 感测电路包括输出节点，并且保险丝盒包括与多个电阻元件串联耦合的多个开关。 保险丝盒耦合到感测电路的输出节点，保险丝盒从该感应电路的输出节点配置为接收电流。 熔丝总线解码器耦合到保险丝盒，并且包括至少一个多路分解器，其被配置为接收信号，并且响应于输出多个控制信号，用于选择性地打开和闭合保险丝盒的开关以调整保险丝盒两端的电阻。 读出放大器的输出节点的电压基于保险丝盒和电流的电阻。

公开(公告)号：US20120057423A1

公开(公告)日：2012-03-08

申请号：US12877646

申请日：2010-09-08

Applicant: Po-Hung CHEN ,  Chin-Huang WANG ,  Yen-Chieh HUANG ,  Sung-Chieh LIN ,  Kuoyuan (Peter) HSU

Inventor： Po-Hung CHEN ,  Chin-Huang WANG ,  Yen-Chieh HUANG ,  Sung-Chieh LIN ,  Kuoyuan (Peter) HSU

IPC: G11C17/16

CPC classification number: G11C17/165

Abstract: Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column.

Abstract translation: 一些实施例涉及具有以行和列，多个位线和多个字线布置的多个eFuse存储器单元的存储器阵列。 列包括位线选择器，耦合到位线选择器的位线和多个eFuse存储器单元。 该列的eFuse存储单元包括PMOS晶体管和eFuse。 PMOS晶体管的漏极耦合到eFuse的第一端。 PMOS晶体管的栅极耦合到字线。 PMOS晶体管的源极耦合到列的位线。

公开(公告)号：US20110273949A1

公开(公告)日：2011-11-10

申请号：US12774851

申请日：2010-05-06

Applicant: Po-Hung CHEN ,  Sung-Chieh LIN ,  Kuoyuan HSU ,  Jiann-Tseng HUANG

Inventor： Po-Hung CHEN ,  Sung-Chieh LIN ,  Kuoyuan HSU ,  Jiann-Tseng HUANG

IPC: G11C17/16

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse.

Abstract translation: 电路包括熔丝和感测和控制电路。 熔丝耦合在MOS晶体管和电流源节点之间。 感测和控制电路被配置为接收编程脉冲并将修改的编程信号输出到MOS晶体管的栅极，以编程保险丝。 改进的编程信号具有基于通过第一保险丝的电流的幅度的脉冲宽度。

公开(公告)号：US20110026354A1

公开(公告)日：2011-02-03

申请号：US12784025

申请日：2010-05-20

Applicant: Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu ,  Jiann-Tseng Huang ,  We-Li Liao

Inventor： Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu ,  Jiann-Tseng Huang ,  We-Li Liao

IPC: G11C5/14 ,  G11C8/00 ,  G11C17/00

CPC classification number: G11C8/12 ,  G11C17/18

Abstract: An OTP memory array includes a bit line coupled to a plurality of memory banks. Each memory bank includes a plurality of memory cells, a footer, and a bias device, and is associated with a current mirror. When a memory cell is activated (e.g., for reading) the memory bank including the activated memory cell is referred to as an activated memory bank and other banks are referred to as deactivated memory banks. A current tracking device serves to compensate for bit line leakage current in deactivated memory cells in the activated memory bank. Further, footers and bias devices in deactivated memory banks and associated current mirrors are configured to reduce/eliminate bit line current leakage through deactivated memory cells in deactivated memory banks.

Abstract translation: OTP存储器阵列包括耦合到多个存储体的位线。 每个存储体包括多个存储单元，一个页脚和一个偏置装置，并与一个电流镜相关联。 当存储器单元被激活（例如，用于读取）时，包括激活的存储器单元的存储体被称为激活的存储体，并且其他存储体被称为去激活存储体。 电流跟踪装置用于补偿激活的存储体中的去激活的存储器单元中的位线泄漏电流。 此外，禁用存储器组和相关联的电流镜中的脚和偏置器件被配置为通过去激活的存储体中的去激活的存储器单元来减少/消除位线电流泄漏。

公开(公告)号：US20070206401A1

公开(公告)日：2007-09-06

申请号：US11368213

申请日：2006-03-02

Applicant: Sung-Chieh Lin ,  Hung-Jen Liao

Inventor： Sung-Chieh Lin ,  Hung-Jen Liao

IPC: G11C5/14 ,  G11C17/00

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: An electrical fuse device includes at least one electrical fuse cell having a first switch device serially coupled with an electrical fuse representing a logic value; and at least one dummy cell having a second switch device coupled to the first switch device via a common word line, the second switch device having a trigger-on voltage lower than that of the first device, such that the second switch becomes conductive earlier than the first switch device for bypassing an electrostatic discharge (ESD) current therethrough during an ESD event.

Abstract translation: 电熔丝装置包括至少一个电熔丝单元，其具有与表示逻辑值的电熔丝串联耦接的第一开关装置; 以及至少一个具有通过公共字线耦合到第一开关装置的第二开关装置的虚拟电池，所述第二开关装置的触发电压低于第一装置的触发电压，使得第二开关比 用于在ESD事件期间绕过静电放电（ESD）电流通过的第一开关装置。

公开(公告)号：US08946825B2

公开(公告)日：2015-02-03

申请号：US13433194

申请日：2012-03-28

Applicant: David Yen ,  Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu

Inventor： David Yen ,  Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu

IPC: H01L23/62

CPC classification number: H01L27/0928 ,  H01L21/263 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0629 ,  H01L29/6609

Abstract: During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.

Abstract translation: 在各种处理操作期间，来自工艺等离子体的离子可以转移到在器件结构下形成的深n阱（DNW）。 反向偏置二极管可以连接到信号线以保护形成在DNW外部的栅极电介质，并且连接到形成在DNW内部的晶体管的漏极。

公开(公告)号：US08767498B2

公开(公告)日：2014-07-01

申请号：US13285357

申请日：2011-10-31

Applicant: Jiann-Tseng Huang ,  Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu

Inventor： Jiann-Tseng Huang ,  Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu

IPC: G11C17/14

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: A circuit includes a fuse circuit and a control circuit. The fuse circuit has an electrical fuse. The control circuit is configured to receive an input signal having an input pulse, and, based on a feedback signal from the fuse circuit, generates a read pulse smaller than the input pulse for use in reading the data stored in the electrical fuse.

Abstract translation: 电路包括熔丝电路和控制电路。 保险丝电路具有电熔丝。 控制电路被配置为接收具有输入脉冲的输入信号，并且基于来自熔丝电路的反馈信号，产生比用于读取存储在电熔丝中的数据的输入脉冲更小的读取脉冲。

公开(公告)号：US08692580B2

公开(公告)日：2014-04-08

申请号：US13407548

申请日：2012-02-28

Applicant: Chen-Ming Hung ,  Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu

Inventor： Chen-Ming Hung ,  Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu

IPC: H03K3/00

CPC classification number: G01R27/08 ,  G11C7/062 ,  G11C17/18 ,  G11C2207/063 ,  H03F3/45179 ,  H03F2200/555 ,  H03F2203/45394 ,  H03F2203/45674

Abstract: An amplifying circuit comprises a bias circuit, a reference circuit, a first circuit, and an amplifying sub-circuit. The bias circuit is configured to provide a bias current. The reference circuit is configured to provide a first differential input based on a reference resistive device and a reference current derived from the bias current. The first circuit is configured to provide a second differential input based on a first current and a first resistance. The amplifying sub-circuit is configured to receive the first differential input and the second differential input and to generate a sense amplifying output indicative of a resistance relationship between the first resistance and a resistance of the reference resistive device.

Abstract translation: 放大电路包括偏置电路，参考电路，第一电路和放大子电路。 偏置电路被配置为提供偏置电流。 参考电路被配置为提供基于参考电阻器件的第一差分输入和从偏置电流导出的参考电流。 第一电路被配置为基于第一电流和第一电阻提供第二差分输入。 放大子电路被配置为接收第一差分输入和第二差分输入，并且产生指示第一电阻和参考电阻器件的电阻之间的电阻关系的读出放大输出。