公开(公告)号：US20190326295A1

公开(公告)日：2019-10-24

申请号：US16107984

申请日：2018-08-21

Applicant: TC Lab, Inc.

Inventor： Harry Luan

IPC: H01L27/108 ,  H01L29/74 ,  H01L29/66 ,  H01L21/02 ,  H01L23/535

Abstract: A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells and associated peripheral circuitry. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Methods of fabricating the array are described.

公开(公告)号：US20190326294A1

公开(公告)日：2019-10-24

申请号：US16007992

申请日：2018-06-13

Applicant: TC Lab, Inc.

Inventor： Harry Luan

IPC: H01L27/108 ,  H01L29/165 ,  H01L29/10 ,  H01L29/74 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells with silicon-germanium base regions. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. Methods of fabricating the array are described.

公开(公告)号：US10453515B2

公开(公告)日：2019-10-22

申请号：US15976706

申请日：2018-05-10

Applicant: TC Lab, Inc.

Inventor： Frank Guo

IPC: G11C11/39 ,  G11C5/14

Abstract: This invention relates to thyristor memory cells with MOS assist gates for enhanced operations. This invention solves various disturb problems in cross point memory array using the thyristor memory cells, including the techniques for protecting stored data inside unselected and half selected bit cells, for recovering weakened stored data in disturbed bit cells, and for effectively shutting off bit cells with minimum disturbance.

公开(公告)号：US10256241B2

公开(公告)日：2019-04-09

申请号：US15426972

申请日：2017-02-07

Applicant: TC Lab, Inc.

Inventor： Harry Luan ,  Valery Axelrad ,  Charlie Cheng

IPC: H01L29/74 ,  H01L31/111 ,  H01L27/102 ,  H01L21/285 ,  H01L21/8229 ,  H01L23/532 ,  H01L29/45 ,  H01L21/02 ,  H01L21/22 ,  H01L21/3205 ,  H01L27/108 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L21/265 ,  H01L29/161 ,  G11C11/39 ,  H01L27/08 ,  H01L29/08 ,  H01L29/87 ,  H01L49/02 ,  H01L29/165

Abstract: Apparatus and methods for reducing minority carriers in a memory array are described herein. Minority carriers diffuse between ON cells and OFF cells, causing disturbances during write operation as well as reducing the retention lifetime of the cells. Minority Carrier Lifetime Killer (MCLK) region architectures are described for vertical thyristor memory arrays with insulation trenches. These MCLK regions encourage recombination of minority carriers. In particular, MCLK regions formed by conductors embedded along the cathode line of a thyristor array, as well as dopant MCLK regions are described, as well as methods for manufacturing thyristor memory cells with MCLK regions.

公开(公告)号：US20180330772A1

公开(公告)日：2018-11-15

申请号：US15976706

申请日：2018-05-10

Applicant: TC Lab, Inc.

Inventor： Frank Guo

IPC: G11C11/39

CPC classification number: G11C11/39 ,  G11C5/14

Abstract: This invention relates to thyristor memory cells with MOS assist gates for enhanced operations. This invention solves various disturb problems in cross point memory array using the thyristor memory cells, including the techniques for protecting stored data inside unselected and half selected bit cells, for recovering weakened stored data in disturbed bit cells, and for effectively shutting off bit cells with minimum disturbance.

公开(公告)号：US20180301455A1

公开(公告)日：2018-10-18

申请号：US16015164

申请日：2018-06-21

Applicant: TC Lab, Inc.

Inventor： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC: H01L27/102 ,  H01L29/66 ,  H01L21/321 ,  H01L21/324 ,  H01L21/762 ,  H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/45

Abstract: Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled with various techniques including encoding the data stored in the arrays.