公开(公告)号：US06809777B2

公开(公告)日：2004-10-26

申请号：US10019419

申请日：2001-12-18

申请人： Hiroyuki Oka ,  Hideshi Nishida ,  Kosuke Yoshioka ,  Tokuzo Kiyohara ,  Makoto Hirai ,  Kozo Kimura ,  Ryuji Matsuura ,  Hiroyuki Morishita ,  Toshiaki Tsuji

发明人： Hiroyuki Oka ,  Hideshi Nishida ,  Kosuke Yoshioka ,  Tokuzo Kiyohara ,  Makoto Hirai ,  Kozo Kimura ,  Ryuji Matsuura ,  Hiroyuki Morishita ,  Toshiaki Tsuji

IPC分类号： H04N964

CPC分类号： H04N19/80 ,  G06T1/20 ,  G06T5/20

摘要： A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group 22 storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supplied from input buffer group 22, and then acquires pixel data from an adjacent pixel processing unit. Further operations are performed by each of the pixel processing units using the acquired pixel data and operation results are accumulated. Filtering is carried out through a repetition of this acquiring and accumulation process, the number of taps being determined by the number of repetitions.

摘要翻译： 用于执行垂直滤波的像素计算装置，其包括16个像素处理单元1至16以及存储16个像素数据和滤波器系数的输入缓冲器组22。 每个像素处理单元使用从输入缓冲器组22提供的像素数据和滤波器系数来执行操作，然后从邻近的像素处理单元获取像素数据。 使用所获取的像素数据由每个像素处理单元执行进一步的操作，并且累积运算结果。 通过重复该获取和累积过程来进行过滤，抽头的数量由重复次数确定。

公开(公告)号：US6105127A

公开(公告)日：2000-08-15

申请号：US920135

申请日：1997-08-27

申请人： Kozo Kimura ,  Tokuzo Kiyohara ,  Kousuke Yoshioka

发明人： Kozo Kimura ,  Tokuzo Kiyohara ,  Kousuke Yoshioka

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/48

CPC分类号： G06F9/4843 ,  G06F9/3009 ,  G06F9/3822 ,  G06F9/3851

摘要： A multithreaded processor for executing multiple instruction streams is provided. This multithreaded processor includes: a plurality of functional units for executing instructions; a plurality of instruction decode units, corresponding to the multiple instruction streams on a one-to-one basis, for respectively decoding an instruction, and producing an instruction issue request for designating to which functional unit the decoded instruction should be issued and requesting for the issuance of the decoded instruction to the designated functional unit; a holding unit for holding the priority level of each instruction stream; and a control unit for deciding which decoded instruction should be issued to a functional unit designated by two or more instruction issue requests at the same time, in accordance with the priority levels held by the holding unit.

摘要翻译： 提供了一种用于执行多个指令流的多线程处理器。 该多线程处理器包括：用于执行指令的多个功能单元; 多个指令解码单元，一对一地对应于多个指令流，用于分别解码指令，并产生指令发出请求，用于指定应该向哪个功能单元发出解码指令，并请求为 向指定的功能单元发出解码指令; 保持单元，用于保持每个指令流的优先级; 以及控制单元，用于根据由保持单元保持的优先级，同时根据由两个或多个指令发出请求指定的功能单元来决定哪个解码指令被发出。

公开(公告)号：US5197136A

公开(公告)日：1993-03-23

申请号：US614680

申请日：1990-11-19

申请人： Kozo Kimura ,  Tokuzo Kiyohara ,  Toshimichi Matsuzaki

发明人： Kozo Kimura ,  Tokuzo Kiyohara ,  Toshimichi Matsuzaki

IPC分类号： G06F9/38

CPC分类号： G06F9/3804

摘要： A storage holds instructions including a branch instruction and a corresponding branch destination instruction. The instructions are sequentially fetched from the storage to a decoder. The decoder sequentially decodes the fetched instructions and derives commands from the respective instructions. The commands are sequentially transferred from the decoder to an execution unit. The execution unit sequentially executes the transferred commands. The decoder serves to detect the branch instruction. When the branch instruction is detected, a normal instruction fetching process is interrupted and the branch destination instruction is promptly fetched to the decoder. The decoder prevents a command of the branch instruction from being transferred to the execution unit.

摘要翻译： 存储器保存包括分支指令和相应的分支目的地指令的指令。 这些指令从存储器顺序取出到解码器。 解码器顺序地对获取的指令进行解码并从相应的指令导出命令。 这些命令从解码器顺序传送到执行单元。 执行单元依次执行传送命令。 解码器用于检测分支指令。 当检测到分支指令时，正常指令取出处理被中断，并且分支目的地指令被迅速地提取到解码器。 解码器防止转移指令的命令被传送到执行单元。

公开(公告)号：US08438523B2

公开(公告)日：2013-05-07

申请号：US13383335

申请日：2011-05-27

申请人： Daisuke Iwahashi ,  Masayoshi Tojima ,  Tokuzo Kiyohara

发明人： Daisuke Iwahashi ,  Masayoshi Tojima ,  Tokuzo Kiyohara

IPC分类号： G06F17/50

CPC分类号： H01L27/0207

摘要： In layout design step of the semiconductor integrated circuit manufacturing method, when it is found that the wiring length between an external terminal and an IO block (external terminal I/F circuit) corresponding to the external terminal increases after a floorplan of a circuit including a functional block and the IO block is determined, placement of the IO block is determined such that the IO block is placed close to the external terminal to alleviate constraints on the wiring between the IO block and the external terminal, and timing adjustment circuits whose number is determined according to the wiring length of a bus (or a shared bus) connecting a data transfer circuit and the IO block is inserted into the bus.

摘要翻译： 在半导体集成电路制造方法的布局设计步骤中，当发现在外部端子与外部端子对应的IO块（外部端子I / F电路）之间的布线长度在包括 功能块和IO块被确定，IO块的放置被确定为使得IO块靠近外部端子放置以减轻对IO块和外部端子之间的布线的约束，以及定时调整电路的数量是 根据将数据传输电路和IO块连接的总线（或共享总线）的布线长度确定为总线。

公开(公告)号：US08082429B2

公开(公告)日：2011-12-20

申请号：US13052281

申请日：2011-03-21

申请人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

发明人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

IPC分类号： G06F9/48

CPC分类号： G06F13/24 ,  G06F9/30101 ,  G06F9/3861 ,  G06F9/3879 ,  G06F9/4812 ,  G06F2209/481

摘要： An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor; a data processing unit that performs particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.

摘要翻译： 信息处理装置执行异常处理程序与正常处理之间的切换。 信息处理装置包括：处理器; 数据处理单元，在从所述处理器接收到处理请求时执行特定处理; 一个向处理器发出中断请求的中断控制器; 以及异常控制单元，其控制所述中断控制器，其中所述数据处理单元经由专用线与所述异常控制单元连接。 数据处理单元包括：通知单元，其经由专用线通知异常控制单元，该异常控制单元指示数据处理单元的当前状态的状态信息，并且基于所通知的状态信息和由处理器设置的设置信息，异常控制 单元判断是否使中断控制器发出中断请求以对处理器执行异常处理程序。

公开(公告)号：US20110173361A1

公开(公告)日：2011-07-14

申请号：US13052281

申请日：2011-03-21

申请人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

发明人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F9/30101 ,  G06F9/3861 ,  G06F9/3879 ,  G06F9/4812 ,  G06F2209/481

摘要： An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor; a data processing unit that performs particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.

摘要翻译： 信息处理装置执行异常处理程序与正常处理之间的切换。 信息处理装置包括：处理器; 数据处理单元，在从所述处理器接收到处理请求时执行特定处理; 一个向处理器发出中断请求的中断控制器; 以及异常控制单元，其控制所述中断控制器，其中所述数据处理单元经由专用线与所述异常控制单元连接。 数据处理单元包括：通知单元，其经由专用线通知异常控制单元，该异常控制单元指示数据处理单元的当前状态的状态信息，并且基于所通知的状态信息和由处理器设置的设置信息，异常控制 单元判断是否使中断控制器发出中断请求以对处理器执行异常处理程序。

公开(公告)号：US07930520B2

公开(公告)日：2011-04-19

申请号：US12110539

申请日：2008-04-28

申请人： Kazushi Kurata ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazuya Furukawa ,  Shigeki Fujii ,  Toshio Sugimura

发明人： Kazushi Kurata ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazuya Furukawa ,  Shigeki Fujii ,  Toshio Sugimura

IPC分类号： G06F9/30 ,  G06F9/44 ,  G06F1/32

CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/462

摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

公开(公告)号：US07779190B2

公开(公告)日：2010-08-17

申请号：US12559916

申请日：2009-09-15

申请人： Tetsuji Mochida ,  Tokuzo Kiyohara ,  Takashi Yamada

发明人： Tetsuji Mochida ,  Tokuzo Kiyohara ,  Takashi Yamada

IPC分类号： G06F13/00

CPC分类号： G06F13/1605

摘要： An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.

摘要翻译： 仲裁装置在主设备之间进行仲裁，使得允许每个主设备以预定带宽访问共享存储器，并且仲裁设备允许设计者在已经设置了访问请求的第一时段中设置访问请求 通过特定的主设备超出已预先分配的带宽。 仲裁设备在跟随第一周期的第二周期中屏蔽来自特定主设备的访问请求。

公开(公告)号：US20090037779A1

公开(公告)日：2009-02-05

申请号：US11916319

申请日：2006-06-06

申请人： Takao Kawakami ,  Masaitsu Nakajima ,  Tokuzo Kiyohara ,  Hiroyuki Morishita ,  Nobuo Higaki ,  Yousuke Kudo

发明人： Takao Kawakami ,  Masaitsu Nakajima ,  Tokuzo Kiyohara ,  Hiroyuki Morishita ,  Nobuo Higaki ,  Yousuke Kudo

IPC分类号： G06F12/00 ,  G06F11/07

CPC分类号： G06F13/385

摘要： In response to a write request from a master to write to an external device, a control unit holds a write address and write data from the master in a write address holding unit and in a write data holding unit, respectively, outputs a reception signal to the master, and writes the write data to the external device specified by the write address. When the master holds the read address in the read address holding unit, the control unit reads data from the external device specified by the read address, and holds the read data in the read data holding unit.

摘要翻译： 响应于来自主机对外部设备的写入请求，控制单元分别保存写入地址并从写入地址保存单元和写入数据保持单元中写入数据，将接收信号输出到 并将写入数据写入由写入地址指定的外部设备。 当主机在读取地址保持单元中保持读取地址时，控制单元从读取地址指定的外部设备读取数据，并将读取的数据保存在读取数据保存单元中。

公开(公告)号：US20080209192A1

公开(公告)日：2008-08-28

申请号：US12110513

申请日：2008-04-28

申请人： Kazuya Furukawa ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazushi Kurata ,  Shigeki Fujii ,  Toshio Sugimura

发明人： Kazuya Furukawa ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazushi Kurata ,  Shigeki Fujii ,  Toshio Sugimura

IPC分类号： G06F9/22

CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/462

摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.