公开(公告)号：US11348869B2

公开(公告)日：2022-05-31

申请号：US17100932

申请日：2020-11-22

Applicant: Unimicron Technology Corp.

Inventor： Chien-Chou Chen ,  Chun-Hsien Chien ,  Wen-Liang Yeh ,  Wei-Ti Lin

IPC: H01L23/04 ,  H01L23/522 ,  H01L23/00 ,  H01L21/50

Abstract: A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.

公开(公告)号：US20220139886A1

公开(公告)日：2022-05-05

申请号：US17125981

申请日：2020-12-17

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming YANG ,  Chen-Hao LIN ,  Chia-Hao CHANG ,  Tzu-Nien LEE

IPC: H01L25/075 ,  H01L33/54 ,  H01L33/62

Abstract: A light-emitting package includes an encapsulating member, a plurality of light-emitting components disposed in the encapsulating member, a plurality of first electrode pads, a plurality of second electrode pads, and a plurality of conductive connection structures. The encapsulating member has a first surface and a second surface opposite to each other. Each light-emitting component has a light-emitting surface exposed on the first surface. Both the first electrode pads and the second electrode pads are exposed on the second surface. A first bonding surface of each first electrode pad and a second bonding surface of each second electrode pad are both flush with the second surface. The light-emitting components disposed on the first electrode pads are electrically connected to the first electrode pads. The conductive connection structures passing through the encapsulating member are electrically connected to the light-emitting components and the second electrode pads.

公开(公告)号：US20220129113A1

公开(公告)日：2022-04-28

申请号：US17113128

申请日：2020-12-07

Applicant: Unimicron Technology Corp.

Inventor： Shih-Yao Lin ,  Ansheng Lee ,  Ming-Yuan Hsu ,  Meng-Chia Chan

IPC: G06F3/044 ,  H01L25/04 ,  H01L25/065 ,  H01L25/075

Abstract: A touch display device includes a flexible substrate, a light emitting structure layer, and a flexible touch sensing layer. The flexible substrate has a first surface and a second surface opposite to each other. The light emitting structure layer is disposed on the first surface of the flexible substrate. The flexible touch sensing layer is disposed on the second surface of the flexible substrate.

公开(公告)号：US11315865B2

公开(公告)日：2022-04-26

申请号：US17234826

申请日：2021-04-20

Applicant: Unimicron Technology Corp.

Inventor： Chien-Chen Lin

IPC: H05K3/06 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11

Abstract: A method of manufacturing circuit board structure includes forming a sacrificial layer having first openings on a substrate; forming a metal layer on the sacrificial layer; forming a patterned photoresist layer having second openings over the sacrificial layer, in which the second openings are connected to the first openings and expose a portion of the metal layer; forming a first circuit layer filling the second openings and the first openings; forming a first dielectric layer over the sacrificial layer and covering the metal layer, in which the first dielectric layer has third openings exposing the first circuit layer; forming a second circuit layer filling the third openings and covering a portion of the first dielectric layer; removing the substrate to expose the sacrificial layer, a portion of the metal layer and a portion of the first circuit layer; and removing the sacrificial layer and the metal layer.

公开(公告)号：US20220068872A1

公开(公告)日：2022-03-03

申请号：US17030380

申请日：2020-09-24

Applicant: Unimicron Technology Corp.

Inventor： Chia-Fu Hsu ,  Kai-Ming Yang ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H01L23/00

Abstract: A fabrication method of an electronic device bonding structure includes the following steps. A first electronic component including a first conductive bonding portion is provided. A second electronic component including a second conductive bonding portion is provided. A first organic polymer layer is formed on the first conductive bonding portion. A second organic polymer layer is formed on the second conductive bonding portion. Bonding is performed on the first electronic component and the second electronic component through the first conductive bonding portion and the second conductive bonding portion, such that the first electronic component and the second electronic component are electrically connected. The first organic polymer layer and the second organic polymer layer diffuse into the first conductive bonding portion and the second conductive bonding portion after the bonding. An electronic device bonding structure is also provided.

公开(公告)号：US20220061157A1

公开(公告)日：2022-02-24

申请号：US17022128

申请日：2020-09-16

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming YANG ,  Chen-Hao LIN ,  Bo-Cheng LIN

IPC: H05K1/11 ,  H05K3/40

Abstract: A wiring board includes a photosensitive insulating layer and a first wiring layer. The photosensitive insulating layer has a hole, a first surface and a second surface opposite to each other. The hole has a first end opening formed in the first surface, a second end opening formed in the second surface, an axis, and a sidewall surrounding the axis. Part of the sidewall extends toward the axis to form at least one annular flange. The first wiring layer is disposed on the first surface and includes a first pad, in which the hole exposes the first pad. There is at least one recessed cavity between the annular flange and the first pad. The minimum width of the annular flange is smaller than the maximum width of the recessed cavity.

公开(公告)号：US20210398925A1

公开(公告)日：2021-12-23

申请号：US17463559

申请日：2021-09-01

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Yu-Chi Shen ,  Tzyy-Jang Tseng ,  Chen-Hua Cheng ,  Pei-Wei Wang

IPC: H01L23/66 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01Q1/22

Abstract: A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.

公开(公告)号：US11166387B2

公开(公告)日：2021-11-02

申请号：US16847688

申请日：2020-04-14

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin ,  Pu-Ju Lin

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H05K3/22

Abstract: A wiring board including a build-up circuit layer, a patterned conductive layer, first and second adhesion promoting material layers and first and second solder mask layers is provided. The build-up circuit layer has a first surface and a second surface opposite thereto. The patterned conductive layer is disposed on the second surface. The first adhesion promoting material layer is disposed on the first surface and includes at least one first opening. The second adhesion promoting material layer is disposed on the second surface and the patterned conductive layer, and includes at least one second opening. The first solder mask layer is disposed on the first adhesion promoting material layer and includes at least one third opening provided corresponding to the first opening. The second solder mask layer is disposed on the second adhesion promoting material layer and includes at least one fourth opening provided corresponding to the second opening.

公开(公告)号：US20210296291A1

公开(公告)日：2021-09-23

申请号：US16846429

申请日：2020-04-13

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang ,  Cheng-Ta Ko

IPC: H01L25/075 ,  H01L33/62 ,  H01L33/52 ,  H01L33/00

Abstract: A manufacturing method of chip package structure includes following steps. A carrier is provided. A first patterned circuit layer and a first dielectric layer covering the first patterned circuit layer have been formed on the carrier. A flat structure layer is formed on the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and covers the flat structure layer and a portion of the first dielectric layer. A second patterned circuit layer is formed on the second dielectric layer. The second patterned circuit layer includes a plurality of pads. An orthographic projection of the flat structure layer on the carrier overlaps orthographic projections of the pads on the carrier. A plurality of chips are disposed on the pads. A molding compound is formed to cover the second dielectric layer and encapsulate the chips and the pads.

公开(公告)号：US20210282277A1

公开(公告)日：2021-09-09

申请号：US17315357

申请日：2021-05-10

Applicant: Unimicron Technology Corp.

Inventor： Wei-Ti Lin ,  Chun-Hsien Chien ,  Fu-Yang Chen

IPC: H05K3/46 ,  H05K3/00 ,  H05K3/40 ,  H05K1/11

Abstract: A circuit carrier board includes a first substrate and a second substrate bonding to the first substrate. The first substrate includes a first circuit layer connecting to a plurality of conductive structure. The conductive structures connect to electronic elements. The second substrate contacts the first circuit layer. The second substrate includes a plurality of stacked dielectric layers, and a plurality of second circuit layers are disposed in the dielectric layers. The bottommost layer of the second circuit layers is exposed outside of the dielectric layers, and the topmost layer of the second circuit layers is electrically connected to the first circuit layer. The conductive structure includes a pad and a conductive via. The pad electrically connects to the first circuit layer. A linewidth of the first circuit layer is smaller than a linewidth of the second circuit layer. A manufacturing method of the circuit carrier board is also provided.