公开(公告)号：US20120054427A1

公开(公告)日：2012-03-01

申请号：US12870566

申请日：2010-08-27

Applicant: WEI-JEN HUANG ,  Chih-Tsung Huang ,  Sachin Agarwal ,  Sha Ma

Inventor： WEI-JEN HUANG ,  Chih-Tsung Huang ,  Sachin Agarwal ,  Sha Ma

IPC: G06F12/00 ,  G06F15/173

CPC classification number: G06F3/061 ,  G06F3/06 ,  G06F3/0659 ,  G06F3/067

Abstract: Techniques are described for increasing data access performance for a memory device. In various embodiments, a scheduler/controller is configured to manage data as it read to or written from a memory. Read access is increased by partitioning a memory into a group of sub-blocks, associating a parity block with the sub-blocks, and accessing the sub-blocks to read data as needed. Write speeds may be improved by adding a pending write buffer to a group of memory sub-blocks. Such a buffer may be sized to be equal to the group of memory sub-blocks. The pending write buffer is used to handle collisions for write accesses to the same block, allowing two simultaneous writes to any regular memory block to occur.

Abstract translation: 描述了用于增加存储器设备的数据访问性能的技术。 在各种实施例中，调度器/控制器被配置为在从存储器读取或从存储器写入时管理数据。 通过将存储器划分成一组子块，将奇偶校验块与子块相关联，以及根据需要访问子块以读取数据来增加读取访问。 通过将一个待处理的写入缓冲区添加到一组存储器子块可以改善写入速度。 这样的缓冲器的大小可以等于存储器子块组。 待处理写缓冲区用于处理对同一块的写入访问的冲突，允许发生任何常规内存块的两次同时写入。

公开(公告)号：US07839167B2

公开(公告)日：2010-11-23

申请号：US12356317

申请日：2009-01-20

Applicant: Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Michael Hutton ,  Victor Maruri ,  Rakesh Patel ,  Peter J. Kazarian ,  Andrew Leaver ,  David W. Mendel ,  Jim Park

Inventor： Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Michael Hutton ,  Victor Maruri ,  Rakesh Patel ,  Peter J. Kazarian ,  Andrew Leaver ,  David W. Mendel ,  Jim Park

IPC: H01L25/00 ,  H03K19/177

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17792

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

Abstract translation: 可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。 在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间，从区域和/或区域之间进行可编程互连。 这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。 例如，这种双形互连资源的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分可具有明显更快的信号速度。 辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

公开(公告)号：US07710091B2

公开(公告)日：2010-05-04

申请号：US11819461

申请日：2007-06-27

Applicant: Wei-Jen Huang

Inventor： Wei-Jen Huang

IPC: G05F1/575

CPC classification number: G05F1/575

Abstract: The present invention discloses an LDO (Low DropOut) linear voltage regulator, which is based on an NMC (Nested Miller Compensation) architecture and can be capacitor-free, wherein an active resistor is added to the feedback path of the Miller compensation capacitor to increase the controllability of the damping factor, solve the problem of extensively using the output capacitor with a parasitic resistance, and solve the problem that a compromise must be made between the damping factor control and the system loop gain. Further, the present invention utilizes a capacitor-sharing technique to reduce the Miller capacitance required by the entire system and accelerate the stabilization of output voltage without influencing stability.

Abstract translation: 本发明公开了一种基于NMC（嵌套米勒补偿）架构的LDO（Low DropOut）线性稳压器，其可以是无电容的，其中有效电阻被添加到Miller补偿电容器的反馈路径中以增加 阻尼因子的可控性解决了使用具有寄生电阻的输出电容器的问题，并解决了阻尼因子控制和系统环路增益之间必须妥协的问题。 此外，本发明利用电容器共享技术来降低整个系统所需的米勒电容，并且加速输出电压的稳定性而不影响稳定性。

公开(公告)号：US20050218930A1

公开(公告)日：2005-10-06

申请号：US11087377

申请日：2005-03-22

Applicant: James Schleicher ,  Jim Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

Inventor： James Schleicher ,  Jim Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

IPC: G06F7/50 ,  G06F7/506 ,  H03K19/173 ,  H03K19/177

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

公开(公告)号：US06912915B2

公开(公告)日：2005-07-05

申请号：US10717511

申请日：2003-11-21

Applicant: Yue-Ying Jian ,  Wen-Sheng Wu ,  Jien-Ren Chen ,  Wei-Jen Huang

Inventor： Yue-Ying Jian ,  Wen-Sheng Wu ,  Jien-Ren Chen ,  Wei-Jen Huang

IPC: G01L1/00 ,  G01N3/08 ,  G01N3/20 ,  G01N33/00 ,  H01L21/66

CPC classification number: G01N3/20

Abstract: An apparatus for shear testing bonds on 8″ and 12″ silicon substrates. The apparatus includes a removable platform for securing the 8″ wafer and a vacuum chuck for securing a 12″ wafer and the removable platform at the same time. A control module controls a moving mechanism to shift a probe to contact the solder ball of the 12″ substrate secured on the vacuum chuck or the solder ball of the 8″ wafer on the removable platform when the removable platform is fixed on the vacuum chuck. The moving mechanism moves the probe in a direction to separate the solder ball from the wafer. A sensor measures the pulling force exerted on the probe when the probe is moved in a direction and separates the solder ball from the wafer.

Abstract translation: 用于在8“和12”硅衬底上进行剪切测试的装置。 该装置包括用于固定8“晶片的可拆卸平台和用于同时固定12”晶片和可移除平台的真空卡盘。 控制模块控制移动机构以移动探头以将固定在真空吸盘上的12“基板的焊球或可移动平台上的8”晶片的焊球接触，当可移动平台固定在真空 卡盘 移动机构使探针沿着使焊球与晶片分离的方向移动。 当探针沿着一个方向移动并将焊球与晶片分离时，传感器测量施加在探针上的拉力。

公开(公告)号：US20050109117A1

公开(公告)日：2005-05-26

申请号：US10717511

申请日：2003-11-21

Applicant: Yue-Ying Jian ,  Wen-Sheng Wu ,  Jien-Ren Chen ,  Wei-Jen Huang

Inventor： Yue-Ying Jian ,  Wen-Sheng Wu ,  Jien-Ren Chen ,  Wei-Jen Huang

IPC: G01L1/00 ,  G01N3/08 ,  G01N3/20 ,  G01N33/00 ,  H01L21/66

CPC classification number: G01N3/20

Abstract: An apparatus for shear testing bonds on 8″ and 12″ silicon substrates. The apparatus includes a removable platform for securing the 8″ wafer and a vacuum chuck for securing a 12″ wafer and the removable platform at the same time. A control module controls a moving mechanism to shift a probe to contact the solder ball of the 12″ substrate secured on the vacuum chuck or the solder ball of the 8″ wafer on the removable platform when the removable platform is fixed on the vacuum chuck. The moving mechanism moves the probe in a direction to separate the solder ball from the wafer. A sensor measures the pulling force exerted on the probe when the probe is moved in a direction and separates the solder ball from the wafer.

Abstract translation: 用于在8“和12”硅衬底上进行剪切测试的装置。 该装置包括用于固定8“晶片的可拆卸平台和用于同时固定12”晶片和可移除平台的真空卡盘。 控制模块控制移动机构以移动探头以将固定在真空卡盘上的12“基板的焊球或可移动平台上的8”晶片的焊球接触，当可移动平台固定在真空 卡盘 移动机构使探针沿着使焊球与晶片分离的方向移动。 当探针沿着一个方向移动并将焊球与晶片分离时，传感器测量施加在探针上的拉力。

公开(公告)号：US06614261B2

公开(公告)日：2003-09-02

申请号：US10047618

申请日：2002-01-14

Applicant: Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

Inventor： Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

IPC: H03K19177

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17792

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

公开(公告)号：US06486702B1

公开(公告)日：2002-11-26

申请号：US09609102

申请日：2000-06-30

Applicant: Tony Ngai ,  Sergey Shumarayev ,  Wei-Jen Huang ,  Rakesh Patel ,  Tin Lai

Inventor： Tony Ngai ,  Sergey Shumarayev ,  Wei-Jen Huang ,  Rakesh Patel ,  Tin Lai

IPC: H03K19177

CPC classification number: G11C5/025 ,  H03K19/17736 ,  H03K19/1776

Abstract: A high-performance programmable logic architecture has embedded memory (608). arranged at the peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements (805) can be directly programmable routed and connected to driver blocks (809) of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources (815, 825). Using similar direct programmable interconnections (828, 830, 835), the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size.

Abstract translation: 高性能可编程逻辑架构具有嵌入式存储器（608）。 布置在集成电路的周边或边缘。 这通过缩短可编程互连（748）的长度来增强可编程逻辑集成电路的性能。 在一个具体实施例中，存储块（703）沿着集成电路的顶部和底部边缘被排列成行。 逻辑元件（805）可以直接编程路由并连接到相邻行和列中的逻辑块的驱动器块（809）。 这允许信号的快速互连，而不使用全局可编程互连资源（815,825）。 使用类似的直接可编程互连（828,88,835），逻辑块可以直接可编程地连接到存储器块而不使用全局可编程互连资源。 本发明还提供了将多个存储器灵活组合或拼接在一起以形成所需尺寸的存储器的技术。

公开(公告)号：US06342792B1

公开(公告)日：2002-01-29

申请号：US09518009

申请日：2000-03-02

Applicant: Wei-Jen Huang ,  Sergey Shumarayev ,  Tony Ngai ,  Bruce Pedersen

Inventor： Wei-Jen Huang ,  Sergey Shumarayev ,  Tony Ngai ,  Bruce Pedersen

IPC: G06F738

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

Abstract: A programmable logic integrated circuit device has logic modules with some inputs that are optimized for speed (to enhance the speed-performance of the logic modules). For example, some of the inputs may be programmably swappable within a logic module so that a speed-critical input signal can be more easily routed to a faster part of the logic module circuitry. Alternatively or in addition, drivers may be added to the logic module circuitry to improve the speed performance of some of the inputs to the logic module. The logic module may be provided with enhanced “lonely register” circuitry which allows the lonely register output signal to be fed back for use as an input to the combinatorial logic of the logic module. The registers in multiple logic modules may be directly chained to one another in a series.

Abstract translation: 可编程逻辑集成电路器件具有逻辑模块，其具有针对速度优化的一些输入（以增强逻辑模块的速度性能）。 例如，一些输入可以在逻辑模块内可编程地交换，使得速度至关重要的输入信号可以更容易地路由到逻辑模块电路的较快部分。 或者或另外，可以将驱动器添加到逻辑模块电路中以提高逻辑模块的一些输入的速度性能。 逻辑模块可以设置有增强的“孤独寄存器”电路，其允许将孤独寄存器输出信号反馈以用作逻辑模块的组合逻辑的输入。 多个逻辑模块中的寄存器可以直接链接到一个系列中。