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    Interconnection and input/output resources for programmable logic integrated circuit devices
    7.
    发明申请
    Interconnection and input/output resources for programmable logic integrated circuit devices 有权
    可编程逻辑集成电路器件的互连和输入/输出资源

    公开(公告)号：US20080074143A1

    公开(公告)日：2008-03-27

    申请号：US11888317

    申请日：2007-07-30

    申请人： Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Michael Hutton ,  Victor Maruri ,  Rakesh Patel ,  Peter Kazarian ,  Andrew Leaver ,  David Mendel ,  Jim Park

    发明人： Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Michael Hutton ,  Victor Maruri ,  Rakesh Patel ,  Peter Kazarian ,  Andrew Leaver ,  David Mendel ,  Jim Park

    IPC分类号： H03K19/177

    CPC分类号： G06F7/506 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17792

    摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

    摘要翻译： 可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。 在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间，从区域和/或区域之间进行可编程互连。 这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。 例如，这种双形互连资源的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分可具有明显更快的信号速度。 辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

    Interconnection resources for programmable logic integrated circuit devices
    8.
    发明授权
    Interconnection resources for programmable logic integrated circuit devices 有权
    可编程逻辑集成电路器件的互连资源

    公开(公告)号：US07262635B2

    公开(公告)日：2007-08-28

    申请号：US11514692

    申请日：2006-09-01

    申请人： James Schleicher ,  Jim Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

    发明人： James Schleicher ,  Jim Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

    IPC分类号： H03K19/177

    CPC分类号： G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

    摘要： A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

    摘要翻译： 可编程逻辑器件具有许多可编程逻辑区域，以及可用于在几乎任何逻辑区域之间进行互连的相对通用的，可编程的互连资源。 此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近的逻辑区域之间建立互连，而不需要使用这些互连的通用互连资源。 本地互连资源通过相对直接的和因此的高速互连来支持逻辑区域的灵活聚集，优选地在逻辑区域的典型二维阵列中的水平和垂直方向。 由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本无边界的。