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    Structure and method for overlay marks
    41.
    发明授权
    Structure and method for overlay marks 有权
    叠加标记的结构和方法

    公开(公告)号：US09543406B2

    公开(公告)日：2017-01-10

    申请号：US13293650

    申请日：2011-11-10

    Applicant: Hsien-Cheng Wang ,  Ming-Chang Wen ,  Chun-Kuang Chen ,  Yao-Ching Ku

    Inventor： Hsien-Cheng Wang ,  Ming-Chang Wen ,  Chun-Kuang Chen ,  Yao-Ching Ku

    IPC: H01L29/66 ,  G03F7/20 ,  H01L29/51

    CPC classification number: H01L22/32 ,  G03F7/70633 ,  H01L21/265 ,  H01L29/517 ,  H01L29/66545

    Abstract: The overlay mark and method for making the same are described. In one embodiment, a semiconductor overlay structure includes gate stack structures formed on the semiconductor substrate and configured as an overlay mark, and a doped semiconductor substrate disposed on both sides of the gate stack structure that includes at least as much dopant as the semiconductor substrate adjacent to the gate stack structure in a device region. The doped semiconductor substrate is formed by at least three ion implantation steps.

    Abstract translation: 对覆盖标记及其制作方法进行说明。 在一个实施例中，半导体覆盖结构包括形成在半导体衬底上并被配置为覆盖标记的栅极叠层结构，以及设置在栅叠层结构两侧的掺杂半导体衬底，其至少包括与半导体衬底相邻的掺杂剂 到设备区域中的栅极堆栈结构。 掺杂半导体衬底通过至少三个离子注入步骤形成。

    Model import for electronic design automation
    42.
    发明授权
    Model import for electronic design automation 有权
    电子设计自动化模型导入

    公开(公告)号：US08352888B2

    公开(公告)日：2013-01-08

    申请号：US13116958

    申请日：2011-05-26

    Applicant: Ru-Gun Liu ,  Chih-Ming Lai ,  Wen-Chun Huang ,  Boren Luo ,  I-Chang Shin ,  Yao-Ching Ku ,  Cliff Hou

    Inventor： Ru-Gun Liu ,  Chih-Ming Lai ,  Wen-Chun Huang ,  Boren Luo ,  I-Chang Shin ,  Yao-Ching Ku ,  Cliff Hou

    IPC: G06F17/50

    CPC classification number: G06F17/50

    Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.

    Abstract translation: 公开了以安全格式提供处理参数的方法和系统。 一方面，公开了一种向设计设备提供半导体制造处理参数的方法。 该方法包括提供制造设施的一组处理参数; 从一组处理参数创建模型; 将模型转换为相应的一组内核; 将所述内核集合转换成相应的矩阵集合; 并将该组矩阵传送到设计设施。 另一方面，公开了一种用于提供半导体制造处理参数的方法。 该方法包括提供制造设施的一组处理参数; 从一组处理参数创建一个处理模型; 将处理模型加密成与多个EDA工具一起使用的格式; 并将加密的处理模型格式传送到设计设施。

    MODEL IMPORT FOR ELECTRONIC DESIGN AUTOMATION
    44.
    发明申请
    MODEL IMPORT FOR ELECTRONIC DESIGN AUTOMATION 有权

    公开(公告)号：US20110230998A1

    公开(公告)日：2011-09-22

    申请号：US13116958

    申请日：2011-05-26

    Applicant: Ru-Gun Liu ,  Chih-Ming Lai ,  Wen-Chun Huang ,  Boren Luo ,  I-Chang Shin ,  Yao-Ching Ku ,  Cliff Hou

    Inventor： Ru-Gun Liu ,  Chih-Ming Lai ,  Wen-Chun Huang ,  Boren Luo ,  I-Chang Shin ,  Yao-Ching Ku ,  Cliff Hou

    IPC: G06F19/00

    CPC classification number: G06F17/50

    Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.

    CD SEM automatic focus methodology and apparatus for constant electron beam dosage control
    46.
    发明授权
    CD SEM automatic focus methodology and apparatus for constant electron beam dosage control 有权
    CD SEM自动聚焦方法和恒电子束剂量控制装置

    公开(公告)号：US06979820B2

    公开(公告)日：2005-12-27

    申请号：US10628914

    申请日：2003-07-29

    Applicant: Chih-Ming Ke ,  Chien-Hsun Lin ,  Yao-Ching Ku

    Inventor： Chih-Ming Ke ,  Chien-Hsun Lin ,  Yao-Ching Ku

    IPC: G01N23/225

    CPC classification number: G01N23/2251

    Abstract: A method and apparatus for scanning electron microscope measurements which maintains a constant e-beam dose to the surface of a wafer being measured and thereby maintains a constant resist shrinkage. The apparatus provides a magnetic lens, a movable wafer holder to adjust the distance between a wafer and the magnetic lens, an image detector, means to determine the distance between the wafer and the magnetic lens, a retarding voltage applied to the wafer holder, means to adjust the retarding voltage, and means to focus the magnetic lens. The apparatus also provides feedback systems between the movable wafer holder and the means to determine the distance between the wafer and the magnetic lens, between the image detector and the means to adjust the retarding voltage, and between the image detector and means to focus the magnetic lens so these adjustments can be made automatically. The method first sets the distance between the wafer and the magnetic lens. The method next determines the charge on the wafer and adjusts the retarding voltage accordingly, thereby maintaining a constant accelerating voltage for the electron beam regardless of charge on the wafer. Finally the method focuses the magnetic objective lens. Maintaining a constant accelerating voltage for the electron beam regardless of charge on the wafer maintains constant resist shrinkage regardless the amount of charge on the wafer.

    Abstract translation: 一种用于扫描电子显微镜测量的方法和装置，其保持对待测晶片的表面的恒定电子束剂量，从而保持恒定的抗蚀剂收缩。 该装置提供磁性透镜，可移动的晶片保持器以调节晶片和磁性透镜之间的距离，图像检测器，确定晶片和磁性透镜之间的距离的装置，施加到晶片保持器的延迟电压，装置 以调节延迟电压，并且意味着聚焦磁性透镜。 该装置还在可移动晶片保持器和用于确定晶片与磁性透镜之间的距离，图像检测器和调节延迟电压的装置之间以及在图像检测器和装置之间聚焦的装置之间提供反馈系统 镜头可以自动进行这些调整。 该方法首先设置晶片和磁性透镜之间的距离。 接下来，该方法确定晶片上的电荷并相应地调整延迟电压，从而保持电子束的恒定的加速电压，而不管晶片上的电荷如何。 最后该方法聚焦磁性物镜。 不管晶片上的电荷量如何，在晶片上保持电子束的恒定加速电压保持恒定的抗蚀剂收缩。

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