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    OPTICAL PROXIMITY CORRECTION CONVERGENCE CONTROL
    1.
    发明申请
    OPTICAL PROXIMITY CORRECTION CONVERGENCE CONTROL 有权
    光临近度校正综合控制

    公开(公告)号：US20130205265A1

    公开(公告)日：2013-08-08

    申请号：US13368919

    申请日：2012-02-08

    Applicant: Cheng-Cheng Kuo ,  Ching-Che Tsai ,  Tzu-Chun Lo ,  Chih-Wei Hsu ,  Hua-Tai Lin ,  Tsai-Sheng Gau ,  Wen-Chun Huang ,  Chih-Shiang Chou ,  Hsin-Chang Lee ,  Kuei Shun Chen

    Inventor： Cheng-Cheng Kuo ,  Ching-Che Tsai ,  Tzu-Chun Lo ,  Chih-Wei Hsu ,  Hua-Tai Lin ,  Tsai-Sheng Gau ,  Wen-Chun Huang ,  Chih-Shiang Chou ,  Hsin-Chang Lee ,  Kuei Shun Chen

    IPC: G06F17/50

    CPC classification number: G03F7/70441 ,  G03F7/70125

    Abstract: A method of optical proximity correction (OPC) convergence control that includes providing a lithography system having a photomask and an illuminator. The method further includes performing an exposure by the illuminator on the photomask. Also, the method includes optimizing an optical illuminator setting for the lithography system with a defined gate pitch in a first direction in a first template. Additionally, the method includes determining OPC correctors to converge the OPC results with a target edge placement error (EPE) to produce a first OPC setting for the first template. The first OPC setting targets a relatively small EPE and mask error enhancement factor (MEEF)of the defined gate pitch in the first template. In addition, the method includes checking the first OPC setting for a relatively small EPE, MEEF and DOM consistency with the first template of the defined gate pitch in a second, adjacent template.

    Abstract translation: 一种光学邻近校正（OPC）会聚控制的方法，包括提供具有光掩模和照明器的光刻系统。 该方法还包括执行照明器在光掩模上的曝光。 此外，该方法包括在第一模板中以第一方向限定的门间距优化光刻系统的光照射器设置。 此外，该方法包括确定OPC校正器以使目标边缘放置误差（EPE）收敛OPC结果，以产生第一模板的第一OPC设置。 第一个OPC设置针对第一个模板中定义的门间距的相对较小的EPE和掩模误差增强因子（MEEF）。 此外，该方法包括在第二相邻模板中检查与相对小的EPE，MEEF和DOM一致性的第一OPC设置与限定的门间距的第一模板。

    N/P BOUNDARY EFFECT REDUCTION FOR METAL GATE TRANSISTORS
    2.
    发明申请
    N/P BOUNDARY EFFECT REDUCTION FOR METAL GATE TRANSISTORS 有权
    N / P边界效应减少金属栅极晶体管

    公开(公告)号：US20130126977A1

    公开(公告)日：2013-05-23

    申请号：US13299152

    申请日：2011-11-17

    Applicant: Hak-Lay Chuang ,  Cheng-Cheng Kuo ,  Ching-Che Tsai ,  Ming Zhu ,  Bao-Ru Young

    Inventor： Hak-Lay Chuang ,  Cheng-Cheng Kuo ,  Ching-Che Tsai ,  Ming Zhu ,  Bao-Ru Young

    IPC: H01L27/092 ,  H01L21/28

    CPC classification number: H01L27/0207 ,  H01L21/0274 ,  H01L21/28123 ,  H01L21/32139 ,  H01L21/823456 ,  H01L27/092 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of dummy gates over a substrate. The dummy gates extend along a first axis. The method includes forming a masking layer over the dummy gates. The masking layer defines an elongate opening extending along a second axis different from the first axis. The opening exposes first portions of the dummy gates and protects second portions of the dummy gates. A tip portion of the opening has a width greater than a width of a non-tip portion of the opening. The masking layer is formed using an optical proximity correction (OPC) process. The method includes replacing the first portions of the dummy gates with a plurality of first metal gates. The method includes replacing the second portions of the dummy gates with a plurality of second metal gates different from the first metal gates.

    Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成多个虚拟栅极。 虚拟门沿着第一轴延伸。 该方法包括在伪栅极上形成掩模层。 掩蔽层限定沿着不同于第一轴线的第二轴线延伸的细长开口。 开口暴露虚拟门的第一部分并保护虚拟门的第二部分。 开口的尖端部分的宽度大于开口的非尖端部分的宽度。 使用光学邻近校正（OPC）工艺形成掩模层。 该方法包括用多个第一金属栅极替换伪栅极的第一部分。 该方法包括用与第一金属栅极不同的多个第二金属栅极替换伪栅极的第二部分。

    Dummy patterns in integrated circuit fabrication
    4.
    发明授权
    Dummy patterns in integrated circuit fabrication 有权
    集成电路制造中的虚拟模式

    公开(公告)号：US07701034B2

    公开(公告)日：2010-04-20

    申请号：US11281030

    申请日：2005-11-17

    Applicant: Harry Chuang ,  Kong-Beng Thei ,  Cheng-Cheng Kuo

    Inventor： Harry Chuang ,  Kong-Beng Thei ,  Cheng-Cheng Kuo

    IPC: H01L27/088

    CPC classification number: H01L27/0207 ,  H01L21/823437 ,  H01L21/823481 ,  Y10S438/926

    Abstract: An embodiment of the invention provides a semiconductor integrated circuit device having a dummy pattern for improving micro-loading effects. The device comprises an active region in a substrate and an isolation region in the substrate adjacent the active region. A plurality of dummy patterns are formed over the isolation region, wherein each dummy pattern is aligned parallel to and lengthwise dimension of the active region. The dummy patterns may have non-uniform spacing or non-uniform aspect ratios. The dummy pattern may have, in plan view, a rectangular shape, wherein its length is greater than the lengthwise dimension of the active region. The spacing between the dummy pattern and the active region may be less than about 1500 nm.

    Abstract translation: 本发明的实施例提供了一种具有用于改善微负载效应的虚拟图案的半导体集成电路器件。 该器件包括衬底中的有源区和邻近有源区的衬底中的隔离区。 在隔离区域上形成多个虚拟图案，其中每个虚拟图案与活动区域平行且纵向尺寸排列。 假图形可以具有不均匀的间隔或不均匀的纵横比。 虚拟图案可以在平面图中具有矩形形状，其长度大于活动区域的纵向尺寸。 虚拟图案和有源区域之间的间隔可以小于约1500nm。

    Dummy patterns in integrated circuit fabrication
    5.
    发明申请
    Dummy patterns in integrated circuit fabrication 有权
    集成电路制造中的虚拟模式

    公开(公告)号：US20060163665A1

    公开(公告)日：2006-07-27

    申请号：US11281030

    申请日：2005-11-17

    Applicant: Harry Chuang ,  Kong-Beng Thei ,  Cheng-Cheng Kuo

    Inventor： Harry Chuang ,  Kong-Beng Thei ,  Cheng-Cheng Kuo

    IPC: H01L29/76

    CPC classification number: H01L27/0207 ,  H01L21/823437 ,  H01L21/823481 ,  Y10S438/926

    Abstract: An embodiment of the invention provides a semiconductor integrated circuit device having a dummy pattern for improving micro-loading effects. The device comprises an active region in a substrate and an isolation region in the substrate adjacent the active region. A plurality of dummy patterns are formed over the isolation region, wherein each dummy pattern is aligned parallel to and lengthwise dimension of the active region. The dummy patterns may have non-uniform spacing or non-uniform aspect ratios. The dummy pattern may have, in plan view, a rectangular shape, wherein its length is greater than the lengthwise dimension of the active region. The spacing between the dummy pattern and the active region may be less than about 1500 nm.

    Abstract translation: 本发明的实施例提供了一种具有用于改善微负载效应的虚拟图案的半导体集成电路器件。 该器件包括衬底中的有源区和邻近有源区的衬底中的隔离区。 在隔离区域上形成多个虚拟图案，其中每个虚拟图案与活动区域平行且纵向尺寸排列。 假图形可以具有不均匀的间隔或不均匀的纵横比。 虚拟图案可以在平面图中具有矩形形状，其长度大于活动区域的纵向尺寸。 虚拟图案和有源区域之间的间隔可以小于约1500nm。

    DUMMY SHOULDER STRUCTURE FOR LINE STRESS REDUCTION
    8.
    发明申请
    DUMMY SHOULDER STRUCTURE FOR LINE STRESS REDUCTION 有权
    用于线应力减少的双层结构

    公开(公告)号：US20110241207A1

    公开(公告)日：2011-10-06

    申请号：US12753272

    申请日：2010-04-02

    Applicant: Cheng Cheng Kuo ,  Luke Lo ,  Minghsing Tsai ,  Ken-Yu Chang ,  Jye-Yen Cheng ,  Jeng-Shiun Ho ,  Hua-Tai Lin ,  Chih-Hsiang Yao

    Inventor： Cheng Cheng Kuo ,  Luke Lo ,  Minghsing Tsai ,  Ken-Yu Chang ,  Jye-Yen Cheng ,  Jeng-Shiun Ho ,  Hua-Tai Lin ,  Chih-Hsiang Yao

    IPC: H01L23/52 ,  G06F17/50

    CPC classification number: H01L21/76838 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.

    Abstract translation: 在本公开中描述了用于改善密集到隔离图案转移区域附近的处理窗口的半导体集成电路线结构和在布局处理中实现线结构的技术。 所公开的结构包括半导体衬底和衬底上方的材料层。 材料层具有紧密间隔的密集线结构，紧密密集线结构旁边的隔离线结构，以及形成在密集线附近和隔离线结构处的虚拟线肩结构。 虚拟线肩结构的一端连接到隔离线结构，另一端以基本垂直于隔离线结构的方向远离隔离线结构延伸。

    Optimized modules' proximity correction
    10.
    发明申请
    Optimized modules' proximity correction 审中-公开
    优化模块的接近校正

    公开(公告)号：US20070083846A1

    公开(公告)日：2007-04-12

    申请号：US11192254

    申请日：2005-07-28

    Applicant: Harry Chuang ,  Cheng-Cheng Kuo

    Inventor： Harry Chuang ,  Cheng-Cheng Kuo

    IPC: G06F17/50

    CPC classification number: G03F1/36

    Abstract: A method comprising dissecting a photomask pattern layout into a plurality of segments, each segment having at least one evaluation point, applying a rule-based MPC to the photomask pattern layout and generating a rule-based MPC result, and applying a model-based MPC to the plurality of segments of the photomask pattern layout and generating an MPC correction that is influenced by the rule-based MPC result.

    Abstract translation: 一种方法，包括将光掩模图案布局解剖成多个段，每个段具有至少一个评估点，将基于规则的MPC应用到光掩模图案布局并生成基于规则的MPC结果，以及应用基于模型的MPC 到光掩模图案布局的多个段，并产生受基于规则的MPC结果影响的MPC校正。

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